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APPENDIX
POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to
●
Accumulator indirect addressing (@A)
Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the
accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB).
Figure B.4-10 Example of Accumulator Indirect Addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
After execution
636
Figure B.4-9 Example of Register List (rlist)
multiple word registers indicated by the register list.)
SP
3 4 F A
× × × ×
RW0
× × × ×
RW1
× × × ×
RW2
× × × ×
RW3
× × × ×
RW4
× × × ×
RW5
× × × ×
RW6
× × × ×
RW7
Memory space
SP
0 1
34FA
H
0 2
34FB
H
0 3
34FC
H
0 4
34FD
H
34FE
H
Before execution
A
0 7 1 6
DTB B B
A
0 7 1 6
DTB B B
SP
3 4 F E
RW0
0 2 0 1
× × × ×
RW1
× × × ×
RW2
× × × ×
RW3
RW4
0 4 0 3
× × × ×
RW5
× × × ×
RW6
× × × ×
RW7
Memory space
0 1
0 2
0 3
0 4
SP
After execution
2 5 3 4
BB2534
BB2535
F F E E
34FA
H
34FB
H
34FC
H
34FD
H
34FE
H
Memory space
E E
H
F F
H
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