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CHAPTER 21 400 kHz I
bit
15
Address:
BER BEIE SCC MSS ACK GCAA INTE
0035A1
H
R/W R/W W R/W
R/W
:
W
:
:
414
2
C INTERFACE
Figure 21.2-2 Configuration of the Bus Control Register
14
13
12
11
10
9
R/W
R/W
R/W R/W
Readable and writable
Write only
Initial value
8
IBCR
INT
Initial value
0 0 0 0 0 0 0 0
B
bit 8
INT
0
see table on next page for details
1
bit 9
INTE
0
Interrupt disabled
1
Interrupt enabled
bit 10
GCCA
Generall call address acknowledge bit
0
No acknowledge on general call address
1
Acknowledge on general call address
bit 11
ACK
0
No Acknowledge on data byte reception
1
Acknowledge on data byte reception
bit 12
MSS
0
Go to slave mode
1
Go to master mode (s. table below for details)
bit 13
SCC
Start condition continue bit
0
Write: No effect:
1
Write: Generate repeated start condition
bit 14
BEIE
Bus error interrupt enable bit
0
Bus error interrupt disabled
1
Bus error interrupt enabled
bit 15
BER
write
0
Clear bus error int.
1
No effect
Interrupt bit
Interrupt enable bit
Acknowledge bit
Master/slave select bit
Bus error bit
read
No error detected
Error detected
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