Serial Input Data Register (Sidr)/Serial Output Data Register (Sodr) - Fujitsu MB91319 Series Hardware Manual

CHAPTER 14 UART
14.2.3 Serial Input Data Register (SIDR)/Serial Output Data
Register (SODR)
These registers are data buffer registers for receiving and sending.

■ Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)

Figure 14.2-4 shows the bit configurations of the serial input data register (SIDR) and the serial
output data register (SODR).
Figure 14.2-4 Bit Configurations of the Serial Input Data Register (SIDR) and the Serial Output
Data Register (SODR)
SIDR
Address: ch0 000061
ch1 000069
ch2 000071
ch3 000079
ch4 000081
SODR
Address: Same as above
These registers are data buffer registers for sending and receiving.
If the data length is seven bits, bit7 (D7) of SIDR and SODR contains invalid data. Accessing
SIDR and SODR when BDS = 1 switches the high-order and low-order data on the bus. As a
result, it appears that bit0 (D0) is ignored.
Write to the SODR register only while the TDRE bit of the SSR register is 1.
Note:
Writing to the register with this address means writing to the SODR register. Reading from the
register with this address means reading from the SIDR register.
264
7 6 5
D7 D6 D5
H
H
R R R
H
H
H
7 6 5
D7 D6 D5
W W W
4 3 2 1
D4 D3 D2 D1
R R R R
4 3 2 1
D4 D3 D2 D1
W W W W
0 Initial value
D0
XXXXXXXX
B
R
0
D0
XXXXXXXX
B
W