Rxusrclk And Rxusrclk2 Generation - Xilinx Virtex-6 FPGA User Manual
Gtx transceivers
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Chapter 4: Receiver
16 to 20 bits, or 32 to 40 bits.
is disabled.
Table 4-57: RX Data Received with 8B/10B Decoder Bypassed
3
3
3
3
3
9
8
7
6
5
Data
Received
RXUSRCLK and RXUSRCLK2 Generation
The FPGA RX interface includes two parallel clocks: RXUSRCLK and RXUSRCLK2.
RXUSRCLK is the internal clock for the PCS logic in the GTX receiver. The required rate for
RXUSRCLK depends on the internal datapath width of the GTXE1 primitive and the RX
line rate of the GTX receiver.
RXUSRCLK.
RXUSRCLK can be generated internally to the GTX transceiver. This functionality is
controlled by the GEN_RXUSRCLK attribute.
RXUSRCLK can be generated internally by the GTX transceiver. In these cases, the
RXUSRCLK port must be tied Low.
Table 4-58: RXUSRCLK Internal Generation Configurations
Notes:
1. For single lane protocols such as 1 Gb/s Ethernet, "GTX Lanes in Channel" is 1. For multiple lane
RXUSRCLK2 is the main synchronization clock for all signals into the RX side of the GTX
transceiver. Most signals into the RX side of the GTX transceiver are sampled on the
positive edge of RXUSRCLK2. RXUSRCLK2 and RXUSRCLK have a fixed-rate
relationship based on the RX_DATA_WIDTH setting.
between RXUSRCLK2 and RXUSRCLK per RX_DATA_WIDTH values.
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Data reception order is right to left
3
3
3
3
3
2
2
2
2
2
4
3
2
1
0
9
8
7
6
5
RXUSRCLK Rate
RX_DATA_WIDTH
1-Byte
8, 10
2-Byte
16, 20
4-Byte
32, 40
protocols like XAUI, "GTX Lanes in Channel" is 2 or more.
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Table 4-57
shows the data received when the 8B/10B decoder
2
2
2
2
2
1
1
1
1
4
3
2
1
0
9
8
7
6
Equation 4-1
shows how to calculate the required rate for
Line Rate
=
------------------------------------------------------------------- -
Internal Datapath Width
Table 4-58
GTX Lanes in Channel
1
2 or more
1 or more
1 or more
Virtex-6 FPGA GTX Transceivers User Guide
< <
1
1
1
1
1
1
9 8 7 6 5 4 3 2 1 0
5
4
3
2
1
0
Equation 4-1
describes the situations in which
(1)
GEN_RXUSRCLK
TRUE
FALSE
TRUE
FALSE
Table 4-59
shows the relationship
UG366 (v2.5) January 17, 2011
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