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Signal Summary
Table 2-1. MPC533 Signal Descriptions (continued)
Signal Name
TCK / DSCK / MCKI
TDO / DSDO / MDO0
JCOMP / RSTI
XTAL
EXTAL
XFC
CLKOUT
EXTCLK
2-10
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
No. of
Function
Type
Signals
after Reset
I
DSCK unless
the Nexus
(READI) port
(MCKI is
I
1
enabled) or
JTAG mode
(TCK is
enabled) is
I
enabled. See
section 25.5.
O
DSDO unless
the Nexus
(READI) port
(MDO[0]) or
O
1
JTAG mode
(TDO) is
enabled. See
section 25.5.
O
JCOMP
unless the
1
I
Nexus
(READI) port
is enabled,
then RSTI.
I
See section
25.5.
Clocks and PLL
1
O
XTAL
1
I
EXTAL
1
I
XFC
1
O
CLKOUT
1
I
EXTCLK
MPC533 Reference Manual
Description
1
Test Clock – This input provides a clock for on-board test
logic (JTAG).
Development Serial Clock – This input signal is the clock
for the debug port interface. See Chapter 23,
"Development Support," for details.
Message Clock In – This input line is the input clock to the
READI module for the NEXUS message clock input.
Test Data Out – This output is used for serial test
instructions and test data for on-board test logic (JTAG).
Development Serial Data Output – This output signal is the
data-out line of the debug port interface. See Chapter 23,
"Development Support," for details.
READI Message Data Out – Message data out: MDO0 is
an output signal used for uploading OTM, BTM, DTM, and
read/write accesses. External latching of MDO occurs on
rising edge of MCKO. Eight MDO signals are implemented.
JTAG Compliancy – This signal enables the IEEE1149.1
JTAG compliant circuitry in the MPC533.
0 JTAG disabled
1 JTAG enabled
RSTI – Reset input for the NEXUS port.
XTAL – This output signal is one of the connections to an
external crystal for the internal oscillator circuitry.
EXTAL – This signal is one of the connections to an
external crystal for the internal oscillator circuitry. If EXTAL
is unused, it must be grounded.
External Filter Capacitance – This input signal is the
connection for an external capacitor filter for the PLL
circuitry.
Clock Out – This output signal is the clock system
frequency. The CLKOUT drive strength can be configured
to full strength, half strength, quarter strength, or disabled.
The drive strength is configured using the COM[0:1] bits
and CQDS bits in the SCCR register in the USIU.
EXTCLK – Input. This is the external frequency source for
the MPC533. If EXTCLK is unused, it must be grounded.
MOTOROLA
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