Block Diagram - Motorola MPC533 Reference Manual

Block Diagram

• One queued serial multi-channel module (QSMCM), which contains one queued
serial peripheral interface (QSPI) and two serial controller interfaces (SCI/UART)
• One peripheral pin multiplexing module (PPM) with a parallel-to-serial driver
• Debug features:
— Nexus debug port (Level 3)
— Background debug mode (BDM)
— IEEE1194.1 compliant interface (JTAG)
• Plastic ball grid array (PBGA) packaging
— 388 ball PBGA
— 27 mm x 27 mm body size
— 1.0 mm ball pitch
• 40-MHz operation
• -40°C–85°C
• Two power supplies
— 5-V I/O (5.0 ± 0.25 V)
— 2.6 ± 0.1-V external bus with a 5-V tolerant I/O system
— 2.6 ± 0.1-V internal logic
— IRAMSTBY on-chip voltage regulator
1.2 Block Diagram
Figure 1-1 is a block diagram of the MPC533.
1-2
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MPC533 Reference Manual MOTOROLA