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2.2
Signal Summary
Table 25-1 describes individual MPC533 signals, grouped by functional module.
Signal Name
ADDR[8:31] / SGPIOA[8:31]
DATA[0:31] / SGPIOD[0:31]
TSIZ[0:1]
RD/WR
BURST
BDIP
TS
TA
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 2-1. MPC533 Signal Descriptions
No. of
Function
Type
Signals
after Reset
Bus Interface
I/O
Controlled by
RCW[SC].
24
See
Table 29-10.
I/O
I/O
Controlled by
RCW[SC].
32
See
Table 29-10.
I/O
2
I/O
TSIZ[0:1]
1
I/O
RD/WR
1
I/O
BURST
1
I/O
BDIP
1
I/O
TS
1
I/O
TA
Chapter 2. Signal Descriptions
Description
1
Address Bus [8:31] – Specifies the physical address of the
bus transaction. The address is driven onto the bus and
kept valid until a transfer acknowledge is received from the
slave. ADDR8 is the MSB for this bus.
Port SGPIOA [8:31] – Allows the signals to be used as
general-purpose inputs/outputs.
Data Bus [0:31] – Provides the general-purpose data path
between the MPC533 and all other devices. Although the
data path is a maximum of 32 bits wide, it can be sized to
support 8-, 16-, or 32-bit transfers. DATA0 is the MSB of
the data bus.
Port SGPIOD [0:31] – Allows the signals to be used as
general-purpose inputs/outputs.
Transfer Size [0:1] – Indicates the size of the requested
data transfer in the current bus cycle.
Read/Write – Indicates the direction of the data transfer for
a transaction. A logic one indicates a read from a slave
device; a logic zero indicates a write to a slave device.
Burst Indicator – Driven by the bus master to indicate that
the currently initiated transaction is a burst.
Burst Data In Progress – Indicates to the slave that there is
a data beat following the current data beat.
Transfer Start – Indicates the start of a bus cycle that
transfers data to/from a slave device. This signal is driven
by the master only when it has gained ownership of the
bus. Every master should negate this signal before
relinquishing the bus. This is an active-low signal and
needs an external pull-up resistor to ensure proper
operation and meet signal timing specifications.
Transfer Acknowledge – This line indicates that the slave
device addressed in the current transaction has accepted
the data transferred by the master (write) or has driven the
data bus with valid data (read). The slave device negates
the TA signal after the end of the transaction. The slave
device will then immediately three-state the TA signal to
prevent contention on the line in case a new transfer that
addresses another slave device(s) is initiated.
This signal is an active-low signal and needs an external
pull-up resistor to ensure proper operation and conform to
signal timing specifications.
Signal Summary
2-3
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