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MSB
1
2
0
Field
SLRC
HRESET
16
17
18
Field
HRESET
Addr
Figure 2-2. Pads Module Configuration Register (PDMCR)
Table 2-5 contains bit descriptions for the PDMCR.
Bits
Name
0
SLRC0 controls the slew rate of signals on the following modules: QADC64E, SGPIOA, SGPIOD,
SGPIOC. For the slew rate refer to Appendix E, "Electrical Characteristics."
0 Slew rate controlled
1 Not slew rate controlled
1
SLRC1 controls the slew rate of signals on the following modules: QSPI and TOUCAN B. For the
slew rate refer to Appendix E, "Electrical Characteristics."
0 Slew rate controlled
1 Not slew rate controlled
2
SLRC2 controls the slew rate of signals on the QSCI in QSMCM . For the slew rate refer to
Appendix E, "Electrical Characteristics."
0 Slew rate controlled
SLRC[0:5]
1 Not slew rate controlled
3
SLRC3 controls the slew rate of signals on the following modules: MIOS14 except
MPWM2/PPM_TX1 and MPWM3 signal. For the slew rate refer to Appendix E, "Electrical
Characteristics."
0 Slew rate controlled
1 Not slew rate controlled
4
SLRC4 controls the slew rate of the MIOS14 MPWM2 signal. For the slew rate refer to Appendix E,
"Electrical Characteristics."
0 Slew rate controlled
1 Not slew rate controlled
5
SLRC5 controls the slew rate of the MIOS14 MPWM3 signal. For the slew rate refer to Appendix E,
"Electrical Characteristics."
0 Slew rate controlled
1 Not slew rate controlled
6
PRDS
Disables weak pull-up/pull down devices enabled at the assertion of PORESET/TRST or HRESET.
Signals affected by the PRDS bit include the following:
• all SGPIO signals
0 Enable weak pull-up/pull down devices on pads controlled by this signal.
1 Disable weak pull-up/pull down devices on pads controlled by this signal.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3
4
5
6
PRDS SPRDS
0000_0000_0000_0000
19
20
21
22
0000_0000_0000_0000
Table 2-5. PDMCR Field Descriptions
Chapter 2. Signal Descriptions
Pad Module Configuration Register (PDMCR)
7
8
9
--
23
24
25
—
0x2F C03C
Description
10
11
12
13
14
PULL_DIS
26
27
28
29
30
15
—
LSB
31
2-23
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