Memory And Bus Architecture; System Architecture; Figure 1. System Architecture - ST STM32F101 Series Reference Manual

Memory and bus architecture

2 Memory and bus architecture
2.1

System architecture

The main system consists of:
Four masters:
–
–
Three slaves:
–
–
–
These are interconnected using a multilayer AHB bus architecture as shown in
Figure 1.
DMA
ICode bus
This bus connects the Instruction bus of the Cortex™-M3 core to the Flash memory
instruction interface. Prefetching is performed on this bus.
DCode bus
This bus connects the DCode bus (literal load and debug access) of the Cortex™-M3 core
to the Flash memory Data interface.
System bus
This bus connects the system bus of the Cortex™-M3 core (peripherals bus) to a BusMatrix
which manages the arbitration between the core and the DMA.
24/501
Cortex™-M3 core ICode bus (I-bus), DCode bus (D-bus), and System bus (S-bus)
GP-DMA (General Purpose DMA)
Internal SRAM
Internal Flash memory
AHB to APB bridges (AHB2APBx) which connect all the APB peripherals
System architecture
DCode
Cortex-M3
System
Ch.1
Ch.2
Ch.7
ICode
FLITF
AHB system bus
Bridge 1
Bridge 2
DMA request
Figure
Flash
memory
SRAM
APB2 APB1
GPIOA USART1 USART2
GPIOB SPI1 USART3
GPIOC ADC1 SPI2
GPIOD ADC2 I2C1
GPIOE TIM1 I2C2
AFIO USB
EXTI
IWDG
RM0008
1:
WWDG
CAN
BKP
PWR
TIM2
TIM3
TIM4