ST STM32F405 Reference Manual page 1062

Secure digital input/output interface (SDIO)
Note: While the SD/SDIO card or MultiMediaCard is in identification mode, the SDIO_CK
frequency must be less than 400 kHz.
The clock frequency can be changed to the maximum card bus frequency when relative
card addresses are assigned to all cards.
After a data write, data cannot be written to this register for three SDIOCLK clock periods
plus two PCLK2 clock periods. SDIO_CK can also be stopped during the read wait interval
for SD I/O cards: in this case the SDIO_CLKCR register does not control SDIO_CK.
31.9.3 SDIO argument register (SDIO_ARG)
Address offset: 0x08
Reset value: 0x0000 0000
The SDIO_ARG register contains a 32-bit command argument, which is sent to a card as
part of a command message.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 CMDARG: Command argument
Command argument sent to a card as part of a command message. If a command contains
an argument, it must be loaded into this register before writing a command to the command
register.
31.9.4 SDIO command register (SDIO_CMD)
Address offset: 0x0C
Reset value: 0x0000 0000
The SDIO_CMD register contains the command index and command type bits. The
command index is sent to a card as part of a command message. The command type bits
control the command path state machine (CPSM).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:15 Reserved, must be kept at reset value
Bit 14 ATACMD: CE-ATA command
Bit 13 nIEN: not Interrupt Enable
Bit 12 ENCMDcompl: Enable CMD completion
1062/1749
Reserved
If ATACMD is set, the CPSM transfers CMD61.
if this bit is 0, interrupts in the CE-ATA device are enabled.
If this bit is set, the command completion signal is enabled.
CMDARG
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RM0090 Rev 18
9 8 7 6 5 4 3
9 8 7 6 5 4 3
RM0090
2 1 0
2 1 0