Table 174. R2 Response; Table 175. R3 Response; Table 176. R4 Response - ST STM32F405 Reference Manual

RM0090
CMD9. Only the bits [127...1] of the CID and CSD are transferred, the reserved bit [0] of
these registers is replaced by the end bit of the response. The card indicates that an erase
is in progress by holding MCDAT low. The actual erase time may be quite long, and the host
may issue CMD7 to deselect the card.
Bit position
135
134
[133:128]
[127:1]
0
31.5.4 R3 (OCR register)
Code length: 48 bits. The contents of the OCR register are sent as a response to CMD1.
The level coding is as follows: restricted voltage windows = low, card busy = low.
Bit position
47
46
[45:40]
[39:8]
[7:1]
0
31.5.5 R4 (Fast I/O)
Code length: 48 bits. The argument field contains the RCA of the addressed card, the
register address to be read from or written to, and its content.
47
46
[45:40]
[39:8] Argument field
Width (bits
1
1
6
127
1
Width (bits
1
1
6
32
7
1
Bit position
[31:16]
[15:8]
[7:0]
Secure digital input/output interface (SDIO)

Table 174. R2 response

Value
0
0
'111111'
X
1

Table 175. R3 response

Value
0
0
'111111'
X
'1111111'
1

Table 176. R4 response

Width (bits
1 0
1 0
6 '100111'
16 X
8 X
8 X
RM0090 Rev 18
Description
Start bit
Transmission bit
Command index
Card status
End bit
Description
Start bit
Transmission bit
Reserved
OCR register
Reserved
End bit
Value Description
Start bit
Transmission bit
CMD39
RCA
register address
read register contents
1055/1749
1075