Clock Security System (Css); Rtc Clock; Watchdog Clock; Clock-Out Capability - ST STM32F101 Series Reference Manual

RM0008
4.2.7

Clock security system (CSS)

Clock Security System can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled, a
clock failure event is sent to the break input of the TIM1 Advanced control timer and an
interrupt is generated to inform the software about the failure (Clock Security System
Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the
Cortex™-M3 NMI (Non-Maskable Interrupt) exception vector.
Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is
automatically generated. The NMI will be executed indefinitely unless the CSS interrupt
pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt
by setting the CSSC bit in the
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock to the HSI oscillator and the disabling of the external
HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL used
as system clock when the failure occurs, the PLL is disabled too.
4.2.8

RTC clock

The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected
by programming the RTCSEL[1:0] bits in the
This selection cannot be modified without resetting the Backup domain.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:
If LSE is selected as RTC clock:
–
If LSI is selected as Auto Wakeup unit (AWU) clock:
–
If the HSE clock divided by 128 is used as RTC clock:
–
4.2.9

Watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
4.2.10

Clock-out capability

The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be
Clock interrupt register
The RTC continues to work even if the V
V supply is maintained.
BAT
The AWU state is not guaranteed if the V
The RTC state is not guaranteed if the V
voltage regulator is powered off (removing power from the 1.8 V domain).
Reset and clock control (RCC)
(RCC_CIR).
Backup domain control register
supply is switched off, provided the
DD
supply is powered off.
DD
supply is powered off or if the internal
DD
(RCC_BDCR).
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