Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1982

ADSP-SC58x PCIE Register Descriptions
Table 29-182: PCIE_PLDBG0_[n] Register Fields (Continued)
Bit No.
(Access)
29–278
Bit Name
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
18 S_L0S For more information see the PCI Express Base
Specification 3.0
19 S_L123_SEND_EIDLE For more information see the
PCI Express Base Specification 3.0
20 S_L1_IDLE For more information see the PCI Express
Base Specification 3.0
21 S_L2_IDLE For more information see the PCI Express
Base Specification 3.0
22 S_L2_WAKE For more information see the PCI Express
Base Specification 3.0
23 S_DISABLED_ENTRY For more information see the
PCI Express Base Specification 3.0
24 S_DISABLED_IDLE For more information see the
PCI Express Base Specification 3.0
25 S_DISABLED For more information see the PCI Ex-
press Base Specification 3.0
26 S_LPBK_ENTRY For more information see the PCI
Express Base Specification 3.0
27 S_LPBK_ACTIVE For more information see the PCI
Express Base Specification 3.0
28 S_LPBK_EXIT For more information see the PCI Ex-
press Base Specification 3.0
29 S_LPBK_EXIT_TIMEOUT For more information see
the PCI Express Base Specification 3.0
30 S_HOT_RESET_ENTRY For more information see
the PCI Express Base Specification 3.0
31 S_HOT_RESET For more information see the PCI Ex-
press Base Specification 3.0
32 S_RCVRY_EQ0 For more information see the PCI Ex-
press Base Specification 3.0
33 S_RCVRY_EQ1 For more information see the PCI Ex-
press Base Specification 3.0
34 S_RCVRY_EQ2 For more information see the PCI Ex-
press Base Specification 3.0
35 S_RCVRY_EQ3 For more information see the PCI Ex-
press Base Specification 3.0