Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2016

ADSP-SC58x PCIE Register Descriptions
Secondary Status and I/O Base and Limit Register
The
PCIE_RC_SECSTAT_[n]
base and limit. This register also provides the upper 4 bits of the 16-bit limit address (bits 15:12) and the upper 4
bits of the 16- bit base address (bits 15:12).
IOLMT (R/W)
I/O Limit
IODEC8 (R/W)
I/O Decode Bit 8
DPE (R/W)
Detected Parity Error
RXSYSERR (R/W)
Received System Error
RXMABRT (R/W)
Received Master Abort
Figure 29-196: PCIE_RC_SECSTAT_[n] Register Diagram
Table 29-205: PCIE_RC_SECSTAT_[n] Register Fields
Bit No.
(Access)
31 DPE
(R/W)
29–312
register provides error and status information for the secondary status and I/O
15 14 13 12 11 10
0 0 0 0 0 0
31 30 29 28 27 26 25
0 0 0 0 0 0
Bit Name
Detected Parity Error.
The PCIE_RC_SECSTAT_[n].DPE bit reports the detection of an address or data
parity error by the bridge on its secondary interface. This bit must be set when any of
the following conditions is true:
• Detects an address parity error as a potential target
• Detects a data parity error when the target of a write transaction
• Detects a data parity error when the master of a read transaction
The bit is set regardless of the state of the PERREN bit (bit 0) in the Bridge Control
register. Once set, this bit remains set until it is reset by writing a 1 to this bit location.
A bridge must implement this bit, and the default state must be 0 after reset.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
9 8 7 6 5 4 3 2
0 1 0 0 0 0 0 0
24 23 22 21 20 19 18 17
0 0 0 0 0 0 0 0
Description/Enumeration
0 Address or data parity error not detected by the bridge
on its secondary interface
1 Address or data parity error detected by the bridge on its
secondary interface
1 0
0 1
IODEC (R/W)
I/O Decode
IOBASE (R/W)
I/O Base
16
0 0
MDPE (R/W)
Master Data Parity Error
STABRT (R/W)
Signaled Target Abort
RXTABRT (R/W)
Received Target Abort