Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2110

NOTE: Refer to the product specific datasheet for exact processor timing.
For the trace length recommendations for the EMAC signals, please refer to the [SYNOPSIS?] datasheet.
For the exact requirements as recommended by the RGMII protocol, please refer to the RGMII specifica-
tion.
Clock Sources
The Ethernet MAC is clocked internally from SCLK0_0. Check the processor data sheet for the valid frequency
range of the appropriate SCLK0_0 signal for Ethernet operation.
Source a 50-MHz clock externally to operate the EMAC in RMII mode. This clock is the same for both transmit
and receive. The MDC station management clock is derived from the SCLK0_0 and driven from the MAC to the
PHY, when accessing any PHY registers. EMAC1 only supports the RMII interface.
Figure 31-7: EMAC Clock Sources for RMII PHY interface
EMAC0 Clock Sources
EMAC0 supports RGMII and RMII interfaces. The external PHY sources a 2.5 MHz or 25 MHz clock (for 10/100
or gigabit Ethernet respectively) to operate the EMAC RXCLK in RGMII mode. The RGMII TXCLK is driven
from CLK07 of the CDU (Clock Distribution Unit) and needs to be configured to 125 MHz regardless of the
EMAC0 speeds (10/100/1000 Mbit/s). The EMAC_MACCFG.PS and EMAC_MACCFG.FES bits are used to di-
vide the clocks down.
For EMAC0 to operate in RMII mode, configuration similar to the one shown in the EMAC Clock Sources for
RGMII PHY Interface is required.
Figure 31-8: EMAC Clock Sources - RGMII PHY Interface
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SCLK
EMAC
CGU
SCLK
CGU
EMAC
CLK07
CDU
EMAC Block Diagram and Interfaces
MDC
PHY
CHIP
RMII REFCLK
50 MHz
OSC
MDC
PHY
CHIP
RGMII TXCLK
RGMII RXCLK
31–19