Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2116

Figure 31-10: EMAC DMA Descriptor Models
Descriptors that reside in the application memory act as pointers to receive and transmit buffers. Descriptors have
the following extra attributes.
• There are two descriptor lists, one for receive, and one for transmit. The base address of each list is written into
the address registers of the receive and transmit descriptor lists respectively.
• A descriptor list is forward linked (either implicitly or explicitly). The last descriptor can point back to the first
entry to create a ring structure.
• Explicit chaining of descriptors is accomplished by setting the second address chained in both receive and
transmit descriptors.
• The descriptor lists reside in the address space of the application memory.
• Each descriptor can point to a maximum of two buffers. This attribute enables two buffers, physically ad-
dressed, rather than contiguous buffers in memory.
A data buffer resides in the physical memory space of the application. It consists of an entire frame or part of a
frame, but cannot exceed a single frame. Buffers can contain only data. The descriptor maintains buffer status. Data
chaining refers to frames that span multiple data buffers. However, a single descriptor cannot span multiple frames.
The DMA skips to the next frame buffer when the end-of-frame is detected. Data chaining is enabled or disabled.
It is possible to define a skip length (in terms of N × 32-bit words) between two subsequent descriptors,
NOTE:
when using ring mode. Program the EMAC_DMA0_BUSMODE.DSL/EMAC_DMA1_BUSMODE.DSL/
EMAC_DMA2_BUSMODE.DSL field to enable this attribute. With this option available, programs are not
always restricted to a contiguous memory location in ring mode.
DMA Related Registers
The Summary of DMA Related Registers table provides a summary of DMA registers relative to their function. Refer
to the "Register Descriptions" sections for complete bit descriptions of each of these registers.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
RING STRUCTURE
BUFFER 1
DESCRIPTOR 0
BUFFER 2
BUFFER 1
DESCRIPTOR 1
BUFFER 2
BUFFER 1
DESCRIPTOR 2
BUFFER 2
BUFFER 1
DESCRIPTOR n
BUFFER 2
CHAIN STRUCTURE
BUFFER 1
DESCRIPTOR 0
BUFFER 1
DESCRIPTOR 1
BUFFER 1
DESCRIPTOR 2
NEXT
DESCRIPTOR
DMA Controller (EMAC DMA)
31–25