Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1957

MSI Controller Interrupt 5 Enable Register
The
PCIE_MSI_IEN5_[n]
bled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI
interrupt vector.
Figure 29-151: PCIE_MSI_IEN5_[n] Register Diagram
Table 29-160: PCIE_MSI_IEN5_[n] Register Fields
Bit No.
(Access)
31:0 EN
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register specifies which interrupts are enabled. When an MSI is received from a disa-
15 14
0 0
EN[15:0] (R/W)
MSI Interrupt 5 Enable
31 30
0 0
EN[31:16] (R/W)
MSI Interrupt 5 Enable
Bit Name
MSI Interrupt 5 Enable.
The PCIE_MSI_IEN5_[n].EN bit field specifies which interrupts are enabled.
13 12 11 10 9 8 7 6
0 0 0 0 0 0 0 0
29 28 27 26 25 24 23 22
0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x PCIE Register Descriptions
5 4 3 2 1 0
0 0 0 0 0 0
21 20 19 18 17 16
0 0 0 0 0 0
29–253