Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2128

Table 31-20: Receive Descriptor Fields (RDES0) (Continued)
Bit Name
7 Time Stamp
Available
6 LC
5 FT
4 RWT
3 Reserved
3 RE
2 DE
1 CE
0 Extended Status
Available
Table 31-21: Receive Descriptor Fields 1 (RDES1)
Bit Name
31 DIC
30–29 Reserved
28–16 RBS2
15 RER
14 RCH
13 Reserved
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
When set, this bit indicates that a snapshot of the time stamp is written in descriptor words 6
(RDES6) and 7 (RDES7). This functionality is valid only when the last descriptor bit (RDES0[8]) is
set
Late Collision. When set, this bit indicates that a late collision has occurred while receiving the
frame in half-duplex mode.
Frame Type. When set, this bit indicates that the receive frame is an Ethernet-type frame (the LT
field is greater than or equal to 16'h0600). When this bit is reset, it indicates that the received frame
is an IEEE802.3 frame. This bit is not valid for runt frames less than 14 bytes.
Receive Watchdog Timeout. When set, this bit indicates that the receive watchdog timer has expired
while receiving the current frame. The current frame is truncated after the watchdog timeout.
Receive Error. When set, this bit indicates that the RGMII PHY sent RGMII RXERR on RXCTL
pin during frame reception. This error also includes the carrier extension error in RGMII and half-
duplex mode.
Dribble Bit Error. When set, this bit indicates that the received frame has a non-integer multiple of
bytes (odd nibbles).
CRC Error. When set, this bit indicates that a Cyclic Redundancy Check (CRC) error occurred on
the received frame. This field is valid only when the last descriptor (RDES0[8]) is set.
When set, this bit indicates that the extended status is available in descriptor word 4 (RDES4). This
functionality is valid only when the last descriptor bit (RDES0[8]) is set.
Description
Disable Interrupt on Completion. When set, this bit prevents setting the EMAC_DMA0_STAT.RI
bit of the status register for the received frame ending in the buffer indicated by this descriptor. This
activity, in turn, disables the assertion of the interrupt to the application due to RI for that frame.
Receive Buffer 2 Size. These bits indicate the second data buffer size, in bytes. The buffer size must
be a multiple of 4 (32-bit bus), even if the value of RDES3 (buffer2 address pointer) does not align
to bus width. If the buffer size is not an appropriate multiple of 4, 8, or 16, the resulting behavior is
undefined. This field is not valid if RDES1[14] is set.
Receive End of Ring. When set, this bit indicates that the descriptor list reached its final descriptor.
The DMA returns to the base address of the list, creating a descriptor ring.
Second Address Chained. When set, this bit indicates that the second address in the descriptor is the
next descriptor address rather than the second buffer address. When this bit is set, RBS2
(RDES1[28:16]) is a do-not-care value. RDES1[15] takes precedence over RDES1[14].
DMA Descriptors
31–37