Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2135

DMA Controller (EMAC DMA)
and RDES3). When either the last data buffer is full or the end-of-frame is reached, DMA clears the
RDES0 [31] bit to 0. Now, the receive descriptor releases to the application for updates
Application Data Buffer Alignment
The transmit and receive data buffers do not have any restrictions on the start address alignment. The start address
for the buffers aligns to any of the 4 bytes. However, the DMA always initiates transfers with the address aligned to
the bus width with dummy data for the byte lanes not required. This alignment typically happens during the trans-
fer of the beginning or end of an Ethernet frame.
Example for Buffer Read
If the transmit buffer address is 0x0002 and 15 bytes must transfer, the DMA reads 5 full words (5 x 32-bit
data) from address 0x0000. However, when transferring data to the EMAC transmit FIFO, the extra bytes
(the first 2 bytes) are dropped or ignored. Similarly, the last 3 bytes of the last transfer are also ignored. The
DMA always transfers a full 32-bit data to the transmit FIFO, unless it is the end-of-frame.
Example for Buffer Write
If the receive buffer address is 0x0002 and 15 bytes of a received frame must transfer, the DMA writes 5 full
words (5 x 32-bit data) to address 0x0000. However, the first 2 bytes of first transfer and the last 3 bytes of the
third transfer have dummy data.
Buffer Size Calculations
The DMA engines do not update the size fields in the transmit and receive descriptors alone. The DMA updates
only the status fields (RDES0 and TDES0) of the descriptors. The driver must perform the size calculations. The
transmit DMA transfers the exact number of bytes (indicated by buffer size field of TDES1) towards the EMAC
CORE. If a descriptor is marked as first (FS bit of TDES1 is set), then the DMA marks the first transfer from the
buffer as the start of frame. If a descriptor is marked as last (LS bit of TDES1), the DMA marks the last transfer
from that data buffer as the end-of frame to the EMAC.
The receive DMA transfers data to a buffer until the buffer is full or the end-of frame is received from the MFL. If a
descriptor is not marked as last (LS bit of RDES0), then the buffers of the descriptor are full. The amount of valid
data in a buffer is its buffer size field minus the data buffer pointer offset, when the FS bit of that descriptor is set.
The offset is zero when the data buffer pointer aligns to the data bus width. If a descriptor is marked as last, then the
buffer cannot be full (as indicated by the buffer size in RDES1). To compute the amount of valid data in this final
buffer, the driver must:
• Read the frame length (FL bits of RDES0 [29:16]), and
• Subtract the sum of the buffer sizes of the preceding buffers in the frame
The receive DMA always transfers the start of next frame with a new descriptor.
EMAC FIFO Layer (EMAC MFL)
The MAC FIFO layer provides FIFO memory to buffer and regulates the frames between the application system
memory and the EMAC CORE. It also allows the transfer of data between the application clock domain and the
31–44 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference