Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2080

ADSP-SC58x TWI Register Descriptions
Table 30-14: TWI_MSTRCTL Register Fields (Continued)
Bit No.
(Access)
0 EN
(R/W)
30–32
Bit Name
Enable Master Mode.
The TWI_MSTRCTL.EN enables master mode functionality. A start condition is gen-
erated if the bus is idle. This bit self clears at the completion of a transfer (after
TWI_MSTRCTL.DCNT decrements to zero), including transfers terminated due to er-
rors.
If disabled (=0) during operation, the transfer is aborted, and all logic associated with
master mode transfers are reset. Serial data and serial clock (SDA, SCL) are no longer
driven. Write-1-to-clear status bits are not affected.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 Disable
1 Enable