Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2018

ADSP-SC58x PCIE Register Descriptions
Table 29-205: PCIE_RC_SECSTAT_[n] Register Fields (Continued)
Bit No.
(Access)
24 MDPE
(R/W)
15:12 IOLMT
(R/W)
8 IODEC8
(R/W)
7:4 IOBASE
(R/W)
0 IODEC
(R/W)
29–314
Bit Name
Master Data Parity Error.
The PCIE_RC_SECSTAT_[n].MDPE bit is used to report the detection of a parity
error by the bridge when it is the master of a transaction. This bit is set if all the fol-
lowing conditions are true:
• The bridge is the bus master of the transaction on the secondary interface.
• The bridge asserted PERR# (read transaction) or detected PERR# asserted (write
transaction).
• The Parity Error Response bit in the Bridge Control register is set.
Once set, this bit remains set until it is reset by writing a 1 to this bit location. A
bridge must implement this bit and the default state must be 0 after reset.
I/O Limit.
The PCIE_RC_SECSTAT_[n].IOLMT bit field contains the upper 4 bits of the
16-bit Limit address (bits 15:12). The lower 12 bits of the limit address are implied to
be all F's.
I/O Decode Bit 8.
I/O Base.
The PCIE_RC_SECSTAT_[n].IOBASE bit field contains the upper 4 bits of the
16-bit Base address (bits 15:12). The lower 12 bits of the base address are implied to
be all 0's, meaning that the base address is always aligned on a 4KB boundary.
I/O Decode.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 No parity error detected on the secondary interface
1 Parity error detected on the secondary interface