Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2113

EMAC System Crossbar Interface (EMAC SCB)
SCB Interface Programming Options
The SCB bus interface supports the following programmable options for the EMAC module. These options are
available using the EMAC_DMA0_BMMODE
programming options apply to DMA1 and DMA2 as well.
• Outstanding transactions. The EMAC-SCB supports up to four outstanding read/write requests on the SCB
bus. Software can control these requests by programming the EMAC_DMA0_BMMODE.WROSRLMT and
EMAC_DMA0_BMMODE.RDOSRLMT bits. Maximum outstanding requests =
EMAC_DMA0_BMMODE.WROSRLMT + 1 (or) EMAC_DMA0_BMMODE.RDOSRLMT + 1.
• Allowed burst sizes. The allowed burst sizes are 4 ( EMAC_DMA0_BMMODE.BLEN4), 8
( EMAC_DMA0_BMMODE.BLEN8), 16 ( EMAC_DMA0_BMMODE.BLEN16) and the SINGLE burst. The
EMAC-SCB uses only those burst sizes configured by the program (through the
ter) for data transfer through the SCB bus. However, SINGLE burst is available by default, when the
EMAC_DMA0_BMMODE.UNDEF bit is cleared. Data transfers are restricted to the maximum burst size from
this list of programmed burst sizes.
• Burst splitting and burst selection. The EMAC-SCB splits the DMA requests into multiple bursts on the SCB
system bus. Splitting is based on DMA count and software controllable burst enable bits (shown in the allowed
burst sizes) as well as burst types (INCR and INCR_ALIGNED). Burst types are also controllable through the
software. SINGLE burst is enabled when the EMAC_DMA0_BMMODE.UNDEF bit is not set. Burst length se-
lect priority is in the sequence: UNDEF, 16, 8, and 4.
• INCR burst type
• If the EMAC_DMA0_BMMODE.UNDEF bit is set, the EMAC-SCB always chooses the maximum allowed
burst length based on the EMAC_DMA0_BMMODE.BLEN16, EMAC_DMA0_BMMODE.BLEN8,
EMAC_DMA0_BMMODE.BLEN4 bits. When the DMA requests are not multiples of the maximum al-
lowed burst length, the SCB can choose a burst-length of any value less than the maximum enabled. (All
lesser burst-length enables are redundant). For example, when length bits are enabled and the DMA re-
quests a burst of 42 beats, the SCB splits it into three bursts of 16, 16 and 10 beats respectively.
• If EMAC_DMA0_BMMODE.UNDEF is not enabled, then the burst length is based on the priority of the
enabled bits in the following order EMAC_DMA0_BMMODE.BLEN16,
EMAC_DMA0_BMMODE.BLEN8, EMAC_DMA0_BMMODE.BLEN4. When the DMA requests a burst
transfer, the SCB interface splits the requested bursts into multiple transfers using only the enabled burst
lengths. This splitting can occur when the requested burst is not a multiple of the maximum enabled
burst. If it cannot choose any of the enabled burst lengths, then it selects the burst length as 1.
For example, the DMA requests a burst transfer of 42 beats, the SCB interface splits it into multiple bursts of
size 16, 16, 8, 1 and 1 beats respectively. (In this case, the allowed burst sizes are enabled and the sequence is in
decreasing burst sizes).
• INCR_ALIGNED burst type. When the address-aligned burst-type is enabled
( EMAC_DMA0_BMMODE.AAL), the SCB interface splits the DMA requested bursts. The "INCR Burst Type"
section explains burst splitting conditions further. Each burst-size aligns to the least significant bits of the start
31–22
register with the EMAC_DMA0_BUSMODE
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register. These
EMAC_DMA0_BMMODE regis-