Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2124

4. If the acquired descriptor is flagged as owned by DMA (TDES0 [31] = 1#b1), the DMA decodes the transmit
data buffer address from the acquired descriptor.
5. The DMA fetches the transmit data from the application memory and transfers the data to the MFL for trans-
mission.
6. If an Ethernet frame is stored over data buffers in multiple descriptors, the DMA closes the intermediate de-
scriptor and fetches the next descriptor. Steps 3, 4, and 5 repeat until the end-of-Ethernet-frame data transfers
to the MFL.
7. Frame transmission completes. If IEEE 1588 time stamping was enabled for the frame, the time stamp value
obtained from MFL is written to the transmit descriptor (TDES2 and TDES3) that contains the end-of-frame
buffer. (The transmit status indicates if IEEE 1588 time stamping enables). The status information is then
written to this transmit descriptor (TDES0). Because the OWN bit is cleared during this step, the application
now owns this descriptor. If time stamping was not enabled for this frame, the DMA does not alter the con-
tents of TDES2 and TDES3.
8. Transmit interrupt (EMAC_DMA0_STAT.TI) is set after completing transmission of a frame. The frame has
interrupt on completion (TDES1 [31]) set in its last descriptor. The DMA engine then returns to Step 3.
9. In the suspend state, the DMA tries to reacquire the descriptor (and returns to Step 3) when it receives a trans-
mit poll demand and the EMAC_DMA0_STAT.UNF bit is cleared.
If the EMAC_DMA0_OPMODE.OSF bit is not set, the actual inter frame gap (IFG) is more than the value
NOTE:
programmed in the
OSF Mode Enabled
While in the run state, the transmit process can simultaneously acquire two frames without closing the status de-
scriptor of the first (if the EMAC_DMA0_OPMODE.OSF bit is set). As the transmit process finishes transferring the
first frame, it immediately polls the transmit descriptor list for the second frame. If the second frame is valid, the
transmit process transfers this frame before writing the status information of the first frame.
In OSF mode, the run state transmit DMA operates in the following sequence.
1. The DMA operates as described in steps 1–6 of
2. Without closing the previous last descriptor of the frame, the DMA fetches the next descriptor.
3. If the DMA owns the acquired descriptor, the DMA decodes the transmit buffer address in this descriptor. If
the DMA does not own the descriptor, the DMA goes into suspend mode and skips to Step 7.
4. The DMA fetches the transmit frame from the application memory and transfers the frame to the MFL until
the end-of-frame data is transferred. It closes the intermediate descriptors when this frame splits across multiple
descriptors.
5. The DMA waits for the frame transmission status and time stamp of the previous frame. Once the status is
available, the DMA writes the time stamp to TDES2 and TDES3, if the time stamp was captured (as indicated
by a status bit). The DMA then writes the status, with a cleared OWN bit, to the corresponding TDES0, thus
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
EMAC_MACCFG register.
Default (Non-OSF) Mode.
Transmit Descriptor
31–33