Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1968

ADSP-SC58x PCIE Register Descriptions
MSI Controller Interrupt 0 Status Register
When an MSI is detected for End Point 0, one bit in the
of the data payload of the MSI memory write request determines which bit is set. A status bit is cleared by writing a
1 to the bit. Each bit corresponds to a single MSI interrupt vector.
VALUE[31:16] (R/W)
MSI Interrupt 0 Status
Figure 29-162: PCIE_MSI_ISTAT0_[n] Register Diagram
Table 29-171: PCIE_MSI_ISTAT0_[n] Register Fields
Bit No.
(Access)
31:0 VALUE
(R/W)
29–264
15
0
VALUE[15:0] (R/W)
MSI Interrupt 0 Status
31
0
Bit Name
MSI Interrupt 0 Status.
The PCIE_MSI_ISTAT0_[n].VALUE bit field indicates when an MSI is detected
for EP0.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PCIE_MSI_ISTAT0_[n]
14 13 12 11 10 9 8 7
0 0 0 0 0 0 0 0
30 29 28 27 26 25 24 23
0 0 0 0 0 0 0 0
Description/Enumeration
register is set. The decoding
6 5 4 3 2 1 0
0 0 0 0 0 0 0
22 21 20 19 18 17 16
0 0 0 0 0 0 0