Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2114

address. The SCB interface initially generates smaller bursts so that the remaining transfers move with the max-
imum (enabled) fixed burst lengths.
For example, in the same setting as explained earlier for EMAC_DMA0_BMMODE.UNDEF set, the DMA re-
quests a burst size of 42 beats at the start address of 0x000003A4.( EMAC_DMA0_BMMODE.BLEN16,
EMAC_DMA0_BMMODE.BLEN8, and EMAC_DMA0_BMMODE.BLEN4 are enabled). The SCB starts the
first transfer with size 3 such that the address of the next burst is aligned (0x000003B0) for a burst of 16.
Therefore, the sequence of bursts is 3, 16, 16, and 7, respectively.
When EMAC_DMA0_BMMODE.UNDEF is not set, then (having a start address of 0x000003A4 with 42 beats),
the sequence of burst transfers is 1, 1, 1, 16, 16, 4, and 3 respectively. The sequence of smaller bursts at the
beginning is used to align the address to the next higher enabled burst-lengths programmed in the register.
• Burst operations for DMA transactions. The EMAC_DMA0_BUSMODE.PBL (programmable burst length)
field indicates the maximum number of beats to transfer in one DMA transaction. This value is also the maxi-
mum used in a single block read/write. It is shown in the following table.
• For example, if EMAC_DMA0_BUSMODE.PBL=32 and if EMAC_DMA0_BMMODE.BLEN16 is enabled,
the DMA automatically splits 32 bursts in to 2 x 16 bursts. If EMAC_DMA0_BUSMODE.PBL=8, and if
EMAC_DMA0_BMMODE.BLEN16 and EMAC_DMA0_BMMODE.BLEN8 are enabled, the maximum
burst is limited to EMAC_DMA0_BMMODE.BLEN8. If the EMAC_DMA0_BUSMODE.PBL8 bit is set,
the programmed EMAC_DMA0_BUSMODE.PBL value is multiplied by 8 times internally. However, the
result cannot be more than the maximum limits specified.
• Set the EMAC_DMA0_BUSMODE.USP bit to make the receive DMA burst length configuration inde-
pendent of the transmit DMA configuration. When this bit is set, the EMAC uses the
EMAC_DMA0_BUSMODE.RPBL bits to define the burst length of receive DMA. If the
EMAC_DMA0_BUSMODE.USP bit is not set, the EMAC_DMA0_BUSMODE.RPBL bits are used for
both transmit and receive. Programs must ensure that the PBL maximum limit is not violated.
• The receive and transmit descriptors are always accessed in the maximum burst-size for the 16-bytes to be
read (PBL-max limit is (TX or RX FIFO size/2)/4 words. (PBL maximum for transmit and receive limits
burst-size).
Table 31-11: DMA PBL Max Limits
Burst Limit Max Term
PBL-maximum limit
PBL-maximum limit (transmit)
PBL-maximum limit (receive)
DMA Bursts Using the SCB Interface
The transmit DMA initiates a data transfer when sufficient space to accommodate the configured burst is available
in the transmit FIFO. Or, the transmit DMA initiates a data transfer when the number of bytes until the end of
frame is less than the configured burst-length. The DMA indicates the start address and the number of transfers
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Definition
(FIFO size/2)/4 words
2048 bytes/2 /4 = 256 words
2048 bytes/2 /4 = 256 words
EMAC System Crossbar Interface (EMAC SCB)
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