Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2105

EMAC Block Diagram and Interfaces
32-BIT
32-BIT
Figure 31-2: EMAC Complete Block Diagram (RGMII, AV Features, and PTP are only available on EMAC0)
EMAC CORE Subblocks
The Core Transmit Engine Subblocks table summarizes the core transmit engine subblocks and their functions. Re-
fer to the EMAC CORE section for further explanation of each of these subblocks.
Table 31-5: CORE Transmit Engine Subblocks
CORE Transmit Engine Sub Block
Transmit Bus Interface
Transmit Frame Controller
Transmit Protocol Engine
Transmit Scheduler
31–14
DMA
INTERRUPT INTERRUPT
LINE
SCLK DOMAIN
SCB RECEIVE
ENGINE
MASTER
INTERFACE
TRANSMIT
ENGINE
BUS MODE
REGISTER
DMA
BUS STATUS
REGISTER CONTROLLER
DMA CONTROL
STATUS
REGISTER
OPERATION
SPB (MMR)
MODE
SLAVE
REGISTER
INTERFACE
EMAC SCB EMAC DMA
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
MMC PTP
AV Channel
INTERRUPT
Bandwidth Status
LINE LINE
INTERRUPT LINE
RxFIFO
MAC Rx
RxFC
TxFIFO
MAC Tx
TxFC
PTP
MMC
AV Feature
EEE
SMI
REGISTERS
MMC
REGISTERS
PTP
REGISTERS
MAC CONTROL
STATUS
REGISTERS
AV Feature
REGISTERS
EEE
REGISTERS
EMAC MFL EMAC CORE
Function
Interface to the FIFO.
Appends Zero-PAD data, if required, for short frames.
Appends CRC for frame checksum from the CRC generator.
Generates preamble and SFD, as per 802.3 protocol.
Generates jam pattern in half-duplex mode, for collisions.
Jabber timeout, for excessively large frames.
Flow control for half-duplex mode (back pressure).
Generates transmit frame status.
Maintains the inter-frame gap between two transmitted frames.
Follows the truncated binary exponential back-off algorithm for
half-duplex mode.
GPIO - PINT
RMI REFCLK (PHYINT)
DOMAIN
RMII /
RMII / RGMII
RGMII
MDIO
PINS
GPIO
MUX