Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2133

Receive Descriptor
8. The receive engine checks the OWN bit of the latest descriptor. If the host owns the descriptor (OWN bit is
0), the EMAC_DMA0_STAT.RU bit is set. The DMA receive engine enters the suspended state (Step 9). If the
DMA owns the descriptor, the engine returns to Step 4 and awaits the next frame.
9. Before the receive engine enters the suspend state, partial frames are flushed from the receive FIFO (programs
control flushing using the EMAC_DMA0_OPMODE.DFF bit).
10. The receive DMA exits the suspend state when a receive poll demand is given or the start of next frame is avail-
able from the receive FIFO of the MFL. The engine proceeds to Step 2 and refetches the next descriptor.
Receive Frame Processing
The EMAC transfers the received frames to the application memory only when:
• the frame passes the address filter subblock, and
• the frame size is greater than or equal to configurable threshold bytes set for the receive FIFO of MFL, or
• the complete frame is written to the FIFO in store-and-forward mode.
If the frame fails the address filtering, the EMAC block drops the frame (unless the EMAC_MACFRMFILT.RA bit
is set). Frames that are shorter than 64 bytes, because of collision or premature termination, can be purged from the
receive FIFO.
After receiving 64 bytes (configurable threshold), the MFL block requests that the DMA block begin transferring
the frame data to the receive buffer pointed to by the current descriptor. The DMA sets first descriptor (RDES0 [9])
after the SCB becomes ready to receive the data (if DMA is not fetching transmit data from the application). The
descriptors release when the OWN (RDES [31]) bit is reset to 0. The bit is reset either as the data buffer fills up or as
the last segment of the frame is transferred to the receive buffer. If the frame is contained in a single descriptor, both
the last descriptor (RDES [8]) and the first descriptor (RDES [9]) are set.
The DMA fetches the next descriptor, sets the last descriptor (RDES [8]) bit, and releases the RDES0 status bits in
the previous frame descriptor. Then, the DMA sets the EMAC_DMA0_STAT.RI bit. The same process repeats un-
less the DMA encounters a descriptor the application owns. If this encounter occurs, the receive process sets the
EMAC_DMA0_STAT.RU bit and then enters the suspend state. The position in the receive list is retained.
Receive Descriptor Acquisition
The receive engine always attempts to acquire an extra descriptor in anticipation of an incoming frame. Descriptor
acquisition is attempted when any of the following conditions is satisfied:
• The EMAC_DMA0_OPMODE.SR bit is set immediately after being placed in the run state.
• The data buffer of current descriptor is full before the frame ends for the current transfer.
• The controller completes frame reception, but the current receive descriptor is not yet closed.
• The receive process suspends because of an application-owned buffer (RDES0 [31] = 0) and a new frame is
received.
• A receive poll demand issues.
31–42 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference