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ADSP-SC58x PCIE Register Descriptions
Port Logic Link Control Register
The
PCIE_PLCTL_[n]
and reset recovery.
FLM (R/W)
Fast Link Mode
DLEN (R/W)
DLL Link Enable
RSTA (R/W)
Reset Assert
LCAPB (R/W)
Link Mode Enable
Figure 29-172: PCIE_PLCTL_[n] Register Diagram
Table 29-181: PCIE_PLCTL_[n] Register Fields
Bit No.
(Access)
21:16
LCAPB
(R/W)
29–274
register controls various functions of the port logic including DLL use, loopback control,
15
14
13
12
11
10
9
8
0
0
0
0
X
X
X
X
31
30
29
28
27
26
25
24
0
0
0
0
X
X
X
X
Bit Name
Link Mode Enable.
The PCIE_PLCTL_[n].LCAPB bit field sets the number of lanes in the link that
are needed to connect to the link partner. When there are unused lanes in a system,
then the value in this bit field must change to reflect the number of lanes.
The value in the "Predetermined Number of Lanes" field of the "Link Width and
Speed Change Control Register" also must change. For more information, see "How to
Tie Off Unused Lanes". For information on upsizing and downsizing the link width,
see "Link Establishment". This register field is sticky.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
7
6
5
4
3
2
1
0
X
X
X
0
X
X
X
X
23
22
21
20
19
18
17
16
0
0
X
X
X
X
X
X
Description/Enumeration
0 x1
1 x2
2 x4
3 x8
4 x16
5 x32 (not supported)
VDLLP (R/W)
Vendor Specific DLLP Request
SDIS (R/W)
Scramble Disable
LPBKEN (R/W)
Loopback Enable
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