Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2024

ADSP-SC58x PCIE Register Descriptions
Latency Timer Register
The
PCIE_RC_TMRLAT_[n]
tency timer value.
SECBUS (R/W)
Secondary Bus Number
TMRSECLAT (R)
Secondary Latency Timer
Figure 29-199: PCIE_RC_TMRLAT_[n] Register Diagram
Table 29-208: PCIE_RC_TMRLAT_[n] Register Fields
Bit No.
(Access)
31:24 TMRSECLAT
(R/NW)
23:16 SUBBUS
(R/W)
15:8 SECBUS
(R/W)
7:0 PRIMBUS
(R/W)
29–320
register provides the primary, secondary and subordinate bus numbers and the la-
15 14 13 12 11 10
0 0 0 0 0 0
31 30 29 28 27 26 25
0 0 0 0 0 0
Bit Name
Secondary Latency Timer.
Subordinate Bus Number.
Secondary Bus Number.
Primary Bus Number.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
9 8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
24 23 22 21 20 19 18 17
0 0 0 0 0 0 0 0
Description/Enumeration
1 0
0 0
PRIMBUS (R/W)
Primary Bus Number
16
0 0
SUBBUS (R/W)
Subordinate Bus Number