Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1949

MSI Controller Lower Address Register
The
PCIE_MSI_CTL_LADDR_[n]
transaction termination. Within the SCB bridge, every received memory write request is examined to see if it targets
the MSI address that has been specified in the MSI Controller Address Register and also to see if it satisfies the
definition of an MSI interrupt request. When these conditions are satisfied the memory write request is marked as
an MSI request.
VALUE[31:16] (R/W)
MSI Controller Lower Address
Figure 29-143: PCIE_MSI_CTL_LADDR_[n] Register Diagram
Table 29-152: PCIE_MSI_CTL_LADDR_[n] Register Fields
Bit No.
(Access)
31:0 VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register contains the system specified lower address for MSI memory write
15
0
VALUE[15:0] (R/W)
MSI Controller Lower Address
31
0
Bit Name
MSI Controller Lower Address.
The PCIE_MSI_CTL_LADDR_[n].VALUE bit field contains the system specified
address for MSI memory write transaction termination.
14 13 12 11 10 9 8 7
0 0 0 0 0 0 0 0
30 29 28 27 26 25 24 23
0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x PCIE Register Descriptions
6 5 4 3 2 1 0
0 0 0 0 0 0 0
22 21 20 19 18 17 16
0 0 0 0 0 0 0
29–245