Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2000

ADSP-SC58x PCIE Register Descriptions
Root Complex Configuration Register
The
PCIE_RC_CFG_[n]
timer.
LATMST_TMR (R)
Latency Master Timer
MULTI_FUNC (R/W)
Multi-function Support
Figure 29-184: PCIE_RC_CFG_[n] Register Diagram
Table 29-193: PCIE_RC_CFG_[n] Register Fields
Bit No.
(Access)
23 MULTI_FUNC
(R/W)
22:16 HDRTYPE
(R/NW)
15:8 LATMST_TMR
(R/NW)
7:0 LNSIZ
(R/W)
29–296
register provides bits to configure the header type, cache line size, and master latency
15 14 13 12 11
0 0 0 0 0
31 30 29 28 27
0 0 0 0 0
Bit Name
Multi-function Support.
This bit must be set to 0.
Header Type.
The PCIE_RC_CFG_[n].HDRTYPE bit field identifies the layout of the second
part of the predefined header and also whether or not the device contains multiple
functions. Bit 7 in this register is used to identify a multifunction device. If the bit is 0,
then the device is single function. If the bit is 1, then the device has multiple func-
tions. Bits 6 through 0 identify the layout of the second part of the predefined header.
Latency Master Timer.
The PCIE_RC_CFG_[n].LATMST_TMR bit field specifies the value of the latency
timer in units of PCI bus clocks.
Cache Line Size.
The PCIE_RC_CFG_[n].LNSIZ bit field specifies the system cache line size in
units of DWORDS.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
10 9 8 7 6 5 4 3
0 0 0 0 0 0 0 0
26 25 24 23 22 21 20 19
0 0 0 0 0 0 0 0
Description/Enumeration
2 1 0
0 0 0
LNSIZ (R/W)
Cache Line Size
18 17 16
0 0 1
HDRTYPE (R)
Header Type