Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2078

ADSP-SC58x TWI Register Descriptions
Master Mode Control Registers
The controls the logic associated with master mode operation. Bits in this register do not affect
TWI_MSTRCTL
slave mode operation and should not be modified to control slave mode functionality.
SCLOVR (R/W)
Serial Clock Override
SDAOVR (R/W)
Serial Data Override
DCNT (R/W)
Data Transfer Count
RSTART (R/W)
Repeat Start
Figure 30-21: TWI_MSTRCTL Register Diagram
Table 30-14: TWI_MSTRCTL Register Fields
Bit No.
(Access)
15 SCLOVR
(R/W)
14 SDAOVR
(R/W)
30–30
15 14 13 12 11 10 9
0 0 0 0 0 0 0
Bit Name
Serial Clock Override.
The TWI_MSTRCTL.SCLOVR provides direct control of the serial clock line when
required. Normal master and slave mode operation should not require override opera-
tion. When TWI_MSTRCTL.SCLOVR is set, the TWI overrides normal serial clock
output, driving it to an active 0 level and overriding all other logic. This state is held
until this bit is cleared. When TWI_MSTRCTL.SCLOVR is cleared, the TWI permits
normal serial clock operation under the control of master mode clock generation and
slave mode clock stretching logic.
Serial Data Override.
The TWI_MSTRCTL.SDAOVR provides direct control of the serial data line when re-
quired. Normal master and slave mode operation should not require override opera-
tion. When TWI_MSTRCTL.SDAOVR is set, the TWI overrides normal serial data
operation under the control of the transmit shift register and acknowledge logic, driv-
ing serial data output to an active 0 level and overriding all other logic. This state is
held until this bit is cleared. When TWI_MSTRCTL.SDAOVR is cleared, the TWI
permits normal serial data operation.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
Description/Enumeration
0 Permit Normal SCL Operation
1 Override Normal SCL Operation
0 Permit Normal SDA Operation
1 Override Normal SDA Operation
0
0
EN (R/W)
Enable Master Mode
DIR (R/W)
Transfer Direction for Master
FAST (R/W)
Fast Mode
STOP (R/W)
Issue Stop Condition