Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2012

ADSP-SC58x PCIE Register Descriptions
Prefetchable Memory Base and Limit Register
The
PCIE_RC_PREFMBL_[n]
BASE (R/W)
Prefetchable Memory Base
LMT (R/W)
Memory Limit
Figure 29-192: PCIE_RC_PREFMBL_[n] Register Diagram
Table 29-201: PCIE_RC_PREFMBL_[n] Register Fields
Bit No.
(Access)
31:20 LMT
(R/W)
16 LMTDEC
(R/NW)
15:4 BASE
(R/W)
0 DEC
(R/W)
29–308
register contains the prefetchable memory base and limit addresses.
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
Bit Name
Memory Limit.
Precethable memory limit
Prefetchable Memory Limit Decode.
Prefetchable memory limit decode
Prefetchable Memory Base.
Prefetchable memory base address
Prefetchable Memory decode.
Prefetchable memory decode
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 1
Description/Enumeration
DEC (R/W)
Prefetchable Memory decode
LMTDEC (R)
Prefetchable Memory Limit Decode