Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2076

ADSP-SC58x TWI Register Descriptions
Table 30-12: TWI_ISTAT Register Fields (Continued)
Bit No.
(Access)
2 SERR
(R/W1C)
1 SCOMP
(R/W1C)
0 SINIT
(R/W1C)
30–28
Bit Name
Slave Transfer Error.
The TWI_ISTAT.SERR indicates that a slave error has occurred. A restart or stop
condition has occurred during the data receive phase of a transfer.
Slave Transfer Complete.
The TWI_ISTAT.SCOMP indicates that the transfer is complete and either a stop, or
a restart was detected.
Slave Transfer Initiated.
The TWI_ISTAT.SINIT indicates whether or not a slave transfer is in progress.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 No Interrupt
1 Interrupt Detected
0 No Interrupt
1 Interrupt Detected
0 No Interrupt. A transfer is not in progress, or an address
match has not occurred since the last time this bit was
cleared.
1 Interrupt Detected. The slave has detected an address
match, and a transfer has been initiated.