Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2108

Table 31-8: RGMII Pins (Continued)
Sl. No. Generic Signal Name (IEEE Standards)
7. MDC
8. MDIO
Figure 31-4: RGMII Data Bit Transfer
PHY Interface Selection
The EMAC1 supports only 10/100 Mbps data-transfer rates with external PHY interfaced through RMII. The
EMAC0 supports both 10/100 Mbps data-transfer rates with external PHY interfaced through RMII and
10/100/1000 Mbps data-transfer rates with external PHY interfaced through RGMII.
Select the external PHY interface for EMAC0 using the
PADS_PCFG0.EMACPHYISEL
PADS_PCFG0.EMACRESET
RGMII Board Design Recommendations
Use the following guidelines during when performing board design when using the RGMII interface.
MAC to PHY (Transmit)
The Ethernet MAC transmits data to the Ethernet PHY. The Ethernet MAC sends data with tskewT (the timing of
TXC at the MAC) that meets the RGMII specification (tskewT = –500 ps to +500 ps skew window for transmitter
to drive data). The RGMII specification requires that at the PHY end, tskewR is sampled at 1.0 to 2.6 ns. According
to the RGMII standard, clocks must be routed such that an additional trace delay of greater than 1.5 ns and less
than 2 ns is added to the associated clock signal.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
BYTE STREAM IN MEMORY
BIT STREAM
D3
TXD[3:0]
D2
D1
RXD[3:0]
D0
RGMII Pin Functionality
Serial management clock driven by EMAC
Serial management bidirectional data
MSB
D7 D6 D5 D4 D3 D2
PADS_PCFG0 register, as shown in the following table.
0 = RMII Interface
1 = RGMII Interface
0 = reset is asserted
1 = reset is deasserted
To select PHY interface, set PADS_PCFG0.EMACPHYISEL bit as
required and then set PADS_PCFG0.EMACRESET.
EMAC Block Diagram and Interfaces
LSB
D1 D0
31–17