Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2148

• Converting the 8-bit stream data to 32-bit data
• Frame filtering
• Attaching the calculated IP checksum
• Updating the receive status
If the EMAC_MACFRMFILT.RA bit is set, the RFC module initiates the data transfer as soon as possible. At the
end of the data transfer, the frame controller sends out the received frame status that includes the address filtering
pass or fail status.
If the EMAC_MACFRMFILT.RA bit is reset, the frame controller performs frame filtering based on the destination
or source address. (The application still must perform another level of filtering if it decides not to receive any bad
frames like runt, CRC error frames, for example.) After receiving the destination or source address bytes, the frame
controller checks the filter-fail signal from the AFM module for an address match. On detecting a filter-fail from
AFM, the frame is dropped and not transferred to the application.
Receive Flow Control Module (FRX)
The receive flow controller detects the receiving pause frame and pauses the frame transmission for the delay speci-
fied within the received pause frame. The flow controller is enabled only in full-duplex mode. The EMAC uses the
EMAC_FLOWCTL.RFE bit to enable or disable the function for pause frame detection.
Once the receive flow control is enabled, the flow controller begins monitoring the received frame destination ad-
dress for any match with the multicast address of the control frame (0x0180C2000001). If a match is detected, it
indicates to the frame controller, that the destination address of the received frame matches the reserved control
frame destination address. The RFC module then decides whether to transfer the received control frame to the ap-
plication, based on the EMAC_MACFRMFILT.PCF bit setting.
The receive flow controller also decodes the type, opcode, and pause timer field of the receiving control frame. The
flow controller requests the MAC transmitter pause the transmission of any data frame.
• If the byte count of the frame status indicates 64 bytes, and
• If there is no CRC error
The transmission is paused for the decoded pause time value, multiplied by the slot time (64-byte times). Mean-
while, if another pause frame is detected with a zero pause time value, the module resets the pause time and gives
another pause request to the transmitter. The module does not generate a pause request to the transmitter:
• If the received control frame does not match the type field (0x8808), opcode (0x00001), or byte length (64
bytes), or
• If there is a CRC error
For a pause frame with a multicast destination address, the frame controller filters the frame based on the address
match from the flow controller. For a pause frame with a unicast destination address, the filtering in the FRX mod-
ule depends on:
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
EMAC CORE Reception Engine
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