Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2022

ADSP-SC58x PCIE Register Descriptions
Table 29-206: PCIE_RC_STATCMD_[n] Register Fields (Continued)
Bit No.
(Access)
6 PERREN
(R/W)
5 VGAPS
(R/NW)
4 MWIE
(R/NW)
3 SCO
(R/NW)
2 BME
(R/W)
1 MSE
(R/W)
0 IOE
(R/W)
29–318
Bit Name
Parity Error Response.
The PCIE_RC_STATCMD_[n].PERREN bit controls the logging of poisoned
TLPs in the PCIE_EP_STATCMD_[n].MSTDPERR bit. A Root Complex Inte-
grated Endpoint that is not associated with a Root Complex Event Collector is permit-
ted to hardwire this bit to 0. Default value of this bit is 0.
VGA Palette Snoop.
Does not apply to PCI Express and must be set to 0.
Memory Write and Invalidate Enable.
Does not apply to PCI Express and must be set to 0.
Special Cycle Operation.
Does not apply to PCI Express and must be set to 0.
Bus Master Enable.
The PCIE_RC_STATCMD_[n].BME bit controls the ability of a PCI Express End-
point to issue Memory and I/O Read/Write Requests, and the ability of a Root or
Switch Port to forward Memory and I/O Read/Write Requests in the Upstream direc-
tion.
For root complex, the PCIE_RC_STATCMD_[n].BME bit controls forwarding of
memory or I/O requests by a switch or root port in the upstream direction. When this
bit is 0, memory and I/O requests received at a root port or the downstream side of a
switch port must be handled as unsupported requests (UR), and for non-posted re-
quests a completion with UR completion status must be returned. This bit does not
affect forwarding of completions in either the upstream or downstream direction. The
forwarding of requests other than memory or I/O requests is not controlled by this bit.
The default value of this bit is 0.
Memory Space Enable.
The PCIE_RC_STATCMD_[n].MSE bit enables memory space.
I/O Space Enable.
The PCIE_RC_STATCMD_[n].IOE bit enables I/O space.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration