Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2106

Table 31-5: CORE Transmit Engine Subblocks (Continued)
CORE Transmit Engine Sub Block
Transmit CRC Generator
Transmit Flow Control
Transmit Checksum Offload Engine
The Core Receive Engine Subblocks table summarizes the core receive engine subblocks and their function. Refer to
the EMAC CORE section for more information on each of these subblocks.
Table 31-6: Core Receive Engine Subblocks
CORE Receive Engine Subblock
Receive Protocol Engine
Receive CRC Module
Receive Frame Controller Module
Receive Flow Control Module
Receive IP Checksum Offload Engine
Receive Bus Interface Unit Module
Address Filtering Module
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Function
Generate CRC for the frame checksum field of the Ethernet frame.
Receives the pause frame, appends the calculated CRC, and sends
the frame to the protocol engine module.
Supports checksum calculation and insertion in the transmit path,
for IPV4/TCP/UDP/ICMP packets.
Functionality Overview
Strips the incoming preamble and SFD.
Checks for correct length or type field.
Performs internal loopback, if necessary.
Generates receive status.
Supports watchdog of received frames.
Supports jumbo frames.
Checks for CRC error, by comparing with FCS.
Packs incoming 8-bit input stream to 32-bit data internally.
Performs frame filtering, for uni-cast, multi-cast, and broadcast
frames.
Attaches the calculated IP checksum input from checksum offload
engine.
Updates the receive status to bus interface.
Detects the receiving pause frame and pauses the frame transmission
for the delay specified within the received pause frame.
Works in full duplex mode.
Calculates IPv4 header checksums and verify against the received
IPv4 header checksums.
Identifies a TCP, UDP, or ICMP payload in the received IP data-
grams.
Interface to the FIFO.
Filters destination and source address based on uni-cast, multi-cast,
and broadcast frames.
Provides CRC hash filtering.
EMAC Block Diagram and Interfaces
31–15