Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2011

Memory Base and Memory Limit Register
The
PCIE_RC_MBL_[n]
memory limit.
Figure 29-191: PCIE_RC_MBL_[n] Register Diagram
Table 29-200: PCIE_RC_MBL_[n] Register Fields
Bit No.
(Access)
31:20 LMT
(R/W)
15:4 BASE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register contains the non-prefetchable memory base address and the non-prefetchable
15 14 13
0 0 0
BASE (R/W)
Memory Base
31 30 29
0 0 0
LMT (R/W)
Memory Limit
Bit Name
Memory Limit.
The PCIE_RC_MBL_[n].LMT bit field contains the non-prefetchable memory lim-
it.
Memory Base.
The PCIE_RC_MBL_[n].BASE bit field contains the non-prefetchable memory
base address.
12 11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
28 27 26 25 24 23 22 21
0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x PCIE Register Descriptions
4 3 2 1 0
0 0 0 0 0
20 19 18 17 16
0 0 0 0 0
29–307