Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2175

EMAC Precision Time Protocol (PTP) Engine
NOTE: A space in the FIFO is created whenever the
the
EMAC_TM_AUXSTMP_NSEC
The program can clear the FIFO by setting the EMAC_TM_CTL.ATSFC bit. When multiple snapshots are present
in the FIFO, the EMAC_TM_STMPSTAT.ATSNS bits indicate the count.
NOTE: The minimum gap between two events on the EMAC_PTPAUXIN[n] pin must be 4 cycles of PTP_CLK
+ 3 cycles of SCLK0_0). Otherwise, the logic misses the rising-edge of the trigger.
System Time
To get a snapshot of the time, the EMAC requires a reference time in 64-bit format as defined in the IEEE 1588
specification. The PTP module maintains 80-bit time, known as system time. The PTP clock updates system time.
The 80-bit timing reference is split into the following three registers:
•
EMAC_TM_NSEC
•
– 32-bit seconds register which provides time in seconds
EMAC_TM_SEC
•
EMAC_TM_HISEC
1588 standard does not include this register. Its use is application-specific.
The 64-bit system time (seconds and nanoseconds) is the source for taking time stamps for Ethernet frames being
transmitted or received at the RMII.
Since the PTP clock frequency does not correspond to a 1ns period, the
with a value equal to the PTP clock period for every PTP clock cycle. The function uses the
register. The
EMAC_TM_NSEC
every PTP clock cycle.
Whenever the
EMAC_TM_SEC
rupt is triggered. The EMAC uses the EMAC_TM_STMPSTAT.TSSOVF bit to indicate the event. After a seconds
overflow, the
EMAC_TM_HISEC
The system time module supports the following two types of rollover modes for the
• Digital rollover mode. The maximum value in the nanoseconds field is 0x3B9AC9FF, that is, 10
After it reaches this value, the
counting from zero. Accuracy in digital rollover mode it is 1 ns per bit.
• Binary rollover mode. The nanoseconds field rolls over and increments the seconds field after the value reaches
0x7FFFFFFF. Accuracy in binary rollover mode is ~0.466 ns per bit.
System Time Adjustment
The following sections describe the process for system time adjustment.
31–84
register before reading the
– 32-bit nanoseconds register which provides time in nanoseconds
– 16-bit high seconds register which provides time beyond the seconds register. The IEEE
value is incremented with the value programmed in
register overflows from 0xFFFFFFFF to 0x00000000, the seconds overflow inter-
register increments by one.
EMAC_TM_SEC
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
EMAC_TM_AUXSTMP_SEC
EMAC_TM_AUXSTMP_SEC
EMAC_TM_NSEC
register increments and the
register is read. Therefore, read
register.
register is incremented
EMAC_TM_SUBSEC
EMAC_TM_SUBSEC
register.
EMAC_TM_NSEC
9
nanoseconds.
EMAC_TM_NSEC register restarts
register