Pin Functions - Analog Devices LTM4683 Manual

PIN FUNCTIONS

PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY .
GND (A1-A4, A7, A12, B1-B4, B7, B12, C3-C4, C7,
C12, D3-D4, D7, D12, E3-E4, E7, E12, F1-F4, F7,
F12, G3-G4, G7, G12, H3-H4, H7, H12, J3-J4, J7,
J12, K1-K4, K7-K12, L1-L15, M1-M15, N1-N4, N7-N8,
N12, P3-P4, P7, P12, R3-R4, R7, R12, T3-T4, T7, T12,
U1-U4, U7, U12, V3-V4, V7, V12, W3-W4, W7, W12,
Y3-Y4, Y7, Y12, AA1-AA4, AA7, AA12, AB1-AB4, AB7,
AB12): Power Ground of the LTM4683. Power return for
V , V , V , and V
IN01 IN23 OUT0,1
output capacitors to this point.
V (A5-A6, B5-B6, C5-C6, D5-D6, E5-E6, F5-F6,
IN01
G5-G6, H5-H6, J5-J6, K5-K6): Positive Power Input to
Channel 0 and Channel 1 Switching Stages. These pins
provide sufficient decoupling capacitance in the form
of multilayer ceramic capacitors (MLCCs) and low ESR
electrolytic (or equivalent) to handle reflected input cur-
rent ripple from the step-down switching stage. MLCCs
should be placed as close to the LTM4683 as physically
possible. See the Layout Checklist/Example section in the
Applications Information section.
VOUT0_CFG (A8): Output Voltage Select Pin for V
Coarse Setting. If the VOUT0_CFG and VTRIM0_CFG pins
are both left open—or, if the LTM4683 is configured to
ignore pin-strap (R
CONFIG
ALL[6] = 1b—then the LTM4683s target V
voltage setting (VOUT_COMMAND0) and associated
power-good and OV/UV warning and fault thresholds are
dictated at SV power-up according to the LTM4683's
IN_01
NVM contents. A resistor divider connected to 2.5V and
to SGND (see Table 1)—in combination with resistor pin
settings on VTRIM0_CFG, and using the factory-default
NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used
to configure the LTM4683's Channel 0 output to power-
up to a VOUT_COMMAND value (and associated output
voltage monitoring and protection/fault-detection thresh-
olds) different from those of NVM contents. (See the
Applications Information section.) Connecting resistor(s)
from VOUT0_CFG to SGND and/or VTRIM0_CFG to SGND
in this manner allows a convenient way to configure
. Return the input and
OUT2,3
) resistors, i.e., MFR_CONFIG_
output
OUT0
For more information
multiple LTM4683s with identical NVM contents for dif-
ferent output voltage settings all without GUI intervention
or the need to custom-preprogram module NVM contents.
Minimize capacitance especially when the pin is left open
to ensure accurate detection of the pin state. Note that
using R s on VOUT0_CFG/VTRIM0_CFG can affect
CONFIG
the V range setting (MFR_PWM_MODE0[1]) and loop
OUT0
gain. For addressed ASEL_01, Page 0x00 corresponds to
Channel 0, and Page 0x01 corresponds to Channel 1. See
PAGE description section.
FSWPH_01_CFG (A9): Switching Frequency, Channel
Phase-Interleaving Angle and Phase Relationship to SYNC
Configuration Pin for Channel 0 and Channel 1. If this pin
is left open—or, if the LTM4683 is configured to ignore
pin-strap (R
CONFIG
1b—then LTM4683's switching frequency (FREQUENCY_
SWITCH) and channel phase relationships (with respect
to the SYNC clock; MFR_PWM_CONFIG[2:0]) are dictated
at SV power-up according to the LTM4683's NVM
IN_01
contents for Channel 0 and Channel 1. Default factory val-
ues are 425kHz operation, Channel 0 at 0°, and Channel 1
at 180°C (convention throughout this document: a phase
angle of 0° means the channel's switch node rises coinci-
dent with the falling edge of the SYNC pulse). Connecting a
,
OUT0
resistor divider from 2.5V to SGND (and using the factory-
default NVM setting of MFR_CONFIG_ALL[6] = 0b) allows
a convenient way to configure multiple LTM4683s with
identical NVM contents for different switching frequencies
of operation and phase interleaving angle settings of intra-
and extra-module-paralleled channels—all, without GUI
intervention or the need to custom pre-program module
NVM contents. (See the Applications Information sec-
tion.) Minimizing capacitance ensures accurate detection
of the pin state.
FAULT0, FAULT1, FAULT2, and FAULT3 (A11, A10, V10,
W10): Digital Programmable FAULT Inputs and Outputs.
Open-drain output. A pull-up resistor to 3.3V is required
in the application.
V (A13-A15, B13-B15, C13-C15, D13-D15, E13-
OUT0
E15): Channel 0 Output Voltage. Place recommended
output capacitors from this shape to GND. See the Layout
Checklist/Example section.
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LTM4683
) resistors, i.e., MFR_CONFIG_ALL[6] =
Rev. 0
15