Pin Functions - Analog Devices Linear LTM 4700 User Manual

PIN FUNCTIONS

PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY .
V (G10): Internally Generated 2.5V Power Supply
DD25
Output Pin. Do not load this pin with external current; it is
used strictly to bias internal logic and provides current for
the internal pull-up resistors connected to the configuration
programming pins. No external decoupling is required.
V (H9): Output Voltage Select Pin for V
TRIM1_CFG
Setting. Works in combination with V
the VOUT_COMMAND (and associated output voltage
monitoring and protection/fault-detection thresholds)
of Channel 1, at SV power-up. (See V
IN
Applications Information section.) Minimize capacitance,
especially when the pin is left open, to assure accurate
detection of the pin state. Note that use of RCONFIGs on
V /V can affect the V
OUT1_CFG TRIM1_CFG
(MFR_PWM_MODE1[1]) and loop gain.
V (H10): Output Voltage Select Pin for V
OUT1_CFG
Course Setting. If the V
OUT1_CFG
both left open, or if the LTM4700 is configured to ignore
pin-strap (R ) resistors (MFR_CONFIG_ALL[6] =
CONFIG
1b), then the LTM4700's target V
setting (VOUT_COMMAND) and associated power-good
and OV/UV warning and fault thresholds are dictated at
S power-up according to the LTM4700's NVM contents.
VIN
A resistor connected from this pin to SGND, in combination
with resistor pin settings on V
factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b
can be used to configure the LTM4700's Channel 1 output
to power-up to a VOUT_COMMAND value (and associated
output voltage monitoring and protection/fault-detection
thresholds) different from those of NVM contents. (See the
Applications Information section.) Connecting resistor(s)
from V to SGND and/or V
OUT1_CFG
this manner allows a convenient way to configure multiple
LTM4700s with identical NVM contents for different output
voltage settings all without GUI intervention or the need to
"custom-pre-program" module NVM contents. Minimize
capacitance, especially when the pin is left open, to as-
sure accurate detection of the pin state. Note that use of
RCONFIGs on V /V
OUT1_CFG
range setting (MFR_PWM_MODE1[1]) and loop gain.
, Fine
OUT1
to affect
OUT1_CFG
and the
OUT1_CFG
range setting
OUT1
OUT1
and V pins are
TRIM1_CFG
output voltage
OUT0
, and using the
TRIM1_CFG
to SGND in
TRIM1_CFG
can affect the V
TRIM1_CFG
For more information
ASEL (H11): Serial Bus Address Configuration Pin. On
2
any given I C/SMBus serial bus segment, every device
must have its own unique slave address. If this pin is
left open, the LTM4700 powers up to a slave address
set by MFR_ADDRESS[6:0] (see Table 4). The factory-
default setting is of 0x4F (hexadecimal), i.e., 1001111b
(industry standard convention is used throughout this
document: 7-bit slave addressing). The lower four bits
of the LTM4700's slave address can be altered from the
NVM-set value by connecting a resistor from this pin to
SGND. Minimize capacitance—especially when the pin is
left open—to assure accurate detection of the pin state.
FAULT0/FAULT1 (H13/H12): Digital Programmable FAULT
Inputs and Outputs. Open-drain output. A pull-up resistor
to 3.3V is required in the application.
SDA (H14): Serial Bus Data Open-Drain Input and Output.
A pull-up resistor to 3.3V is required in the application.
WP (J8): Write Protect Pin, Active High. An internal 10µA
,
current source pulls this pin to V
or logic high, only I
FAULTS, MFR_CLEAR_PEAKS and MFR_EE_UNLOCK are
supported. Additionally, Individual faults can be cleared
by writing 1b's to bits of interest in registers prefixed with
"STATUS". If WP is low, I
V (J9): Output Voltage Select Pin for V
TRIM0_CFG
Setting. Works in combination with V
the VOUT_COMMAND (and associated output voltage
monitoring and protection/fault-detection thresholds)
of Channel 0, at SV
Applications Information section.) Minimize capacitance,
especially when the pin is left open, to assure accurate
detection of the pin state. Note that use of RCONFIGs on
V /V
OUT0_CFG TRIM0_CFG
(MFR_PWM_MODE0[1]) and loop gain.
V (J10): Output Voltage Select Pin for V
OUT0_CFG
Course Setting. If the V
both left open, or if the LTM4700 is configured to ignore
pin-strap (R
CONFIG
1b), then the LTM4700's target V
ting (VOUT_COMMAND) and associated power-good and
OV/UV warning and fault thresholds are dictated at SV
OUT1
power-up according to the LTM4700's NVM contents.
www.analog.com
LTM4700
. If WP is open circuit
DD33
2
C writes to PAGE, OPERATION, CLEAR_
2
C writes are unrestricted.
OUT0_CFG
power-up. (See V
IN OUT0_CFG
can affect the V
OUT0
and V
OUT0_CFG TRIM0_CFG
) resistors (MFR_CONFIG_ALL[6] =
output voltage set-
OUT0
, Fine
OUT0
to affect
and the
range setting
,
OUT0
pins are
IN
Rev. B
15