Pin Functions - Analog Devices ADAV4622 Manual

PIN FUNCTIONS

Table 5 shows the pin numbers, mnemonics, and descriptions
for the ADAV4622. The input pins have a logic threshold
compatible with 3.3 V input levels.
SDIN0, SDIN1, SDIN2, AND SDIN3/SPDIF_IN0
Serial data inputs. These input pins provide the digital audio
data to the signal processing core. Any of the inputs can be
routed to either of the SRCs for conversion; this input is then
not available as a synchronous input to the audio processor but
only as an input through the selected SRC. The serial format
for the synchronous data is selected by Bits [3:2] of the serial
port control register. If the SRCs are required, the serial format
is selected by Bits [12:9] of the same register. The synchronous
inputs are capable of using any pair of serial clocks LRCLK0/
BCLK0, LRCLK1/BCLK1, or LRCLK2/BCLK2. By default,
they use LRCLK1 and BCLK1. See Figure 24 for more details
regarding the configuration of the synchronous inputs.
SDIN3 is a shared pin with SPDIF_IN0. If SDIN3 is not in use,
this pin can be used to connect an S/PDIF signal from an
external source, such as an MPEG decoder, to the ADAV4622
on-chip S/PDIF output multiplexer. If SPDIF_OUT is selected
from one of the SPDIF_IN (external) signals, the signal is
simply passed through from input to output.
LRCLK0, BCLK0, LRCLK1, BCLK1, LRCLK2, AND
BCLK2
By default, LRCLK1 and BCLK1 are associated with the
synchronous inputs, LRCLK0 and BCLK0 are associated with
SRC1, and LRCLK2 and BCLK2 are associated with SRC2.
However, the SRCs and synchronous inputs can use any of the
serial clocks (see Figure 24 for more details). LRCLK0, BCLK0,
LRCLK1, BCLK1, LRCLK2, and BCLK2 are shared pins with
SPDIF_IN1, SPDIF_IN2, SPDIF_IN3, SPDIF_IN4, SPDIF_IN5,
and SPDIF_IN6, respectively. If LRCLK0/LRCLK1/LRCLK2 or
BCLK0/BCLK1/BCLK2 are not in use, these pins can be used to
connect an S/PDIF signal from an external source, such as an
MPEG decoder, to the ADAV4622 on-chip S/PDIF output
multiplexer. If SPDIF_OUT is selected from one of the
SPDIF_IN (external) signals, the signal is simply passed
through from input to output.
SDO0/AD0
Serial data output. This pin can output two channels of digital
audio using a variety of standard 2-channel formats. The clocks
for SDO0 are always the same as those used by the synchronous
inputs; this means that LRCLK1 and BCLK1 are used by default,
although SDO0 is capable of using any pair of serial clocks,
LRCLK0/BCLK0, LRCLK1/BCLK1, or LRCLK2/BCLK2.
The serial port control register selects the serial format for the
synchronous output. On reset, the SDO0 pin duplicates as the
2
I C® address select pin. In this mode, the logical state of the pin
is polled for four MCLKI cycles following reset. The address
select bit is set as the majority poll of the pin's logic level after
the four MCLKI cycles.
SPDIF_OUT (SDO1)
The ADAV4622 contains an S/PDIF multiplexer functionality
that allows the SPDIF_OUT signal to be chosen from an
internally generated S/PDIF signal or from the S/PDIF signal
from an external source, which is connected via one of the
SPDIF_IN pins. This pin can also be configured as an
additional serial data output (SDO1) as an alternate function.
MCLKI/XIN
Master clock input. The ADAV4622 uses a PLL to generate the
appropriate internal clock for the audio processing core. A clock
signal of a suitable frequency can be connected directly to this
pin, or a crystal can be connected between MCLKI/XIN and
XOUT together with the appropriate capacitors to DGND to
generate a suitable clock signal.
XOUT
This pin is used in conjunction with MCLKI/XIN to generate a
clock signal for the ADAV4622.
MCLK_OUT
This pin can be used to output MCLKI or one of the internal
system clocks. It should be noted that the output level of this
pin is referenced to DVDD (1.8 V) and not ODVDD (3.3 V)
like all other digital inputs and outputs.
SDA
Serial data input for the I
elimination filter that removes spurious pulses that are less than
50 ns wide.
Rev. B | Page 19 of 28
ADAV4622
2
C control port. SDA features a glitch