STMicroelectronics STM32WLEx Reference Manual page 1070

Universal synchronous/asynchronous receiver transmitter (USART/UART)
33.8.2 USART control register 1 [alternate] (USART_CR1)
Address offset: 0x00
Reset value: 0x0000 0000
The same register can be used in FIFO mode enabled (previous section) and FIFO mode
disabled (this section).
FIFO mode disabled
31 30 29
FIFO
Res. Res.
EN
rw
15 14 13
OVER8 CMIE MME
rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 FIFOEN: FIFO mode enable
This bit is set and cleared by software.
0: FIFO mode is disabled.
1: FIFO mode is enabled.
This bitfield can only be written when the USART is disabled (UE = 0).
Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode
Bit 28 M1: Word length
This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or
cleared by software.
M[1:0] = '00': 1 start bit, 8 Data bits, n Stop bit
M[1:0] = '01': 1 start bit, 9 Data bits, n Stop bit
M[1:0] = '10': 1 start bit, 7 Data bits, n Stop bit
This bit can only be written when the USART is disabled (UE = 0).
Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate
Bit 27 EOBIE: End of Block interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at
Bit 26 RTOIE: Receiver timeout interrupt enable
This bit is set and cleared by software.
0: Interrupt inhibited
1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
1070/1306
28 27 26 25
M1 EOBIE RTOIE
rw rw rw rw
12 11 10 9
M0 WAKE PCE PS
rw rw rw rw
and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
(0x7F and 0x55 frames detection) are not supported.
reset value. Refer to
must be kept at reset value.
24 23 22
DEAT[4:0]
rw rw rw
8 7 6
PEIE TXEIE TCIE
rw rw rw
Section 33.4: USART implementation on page
Section 33.4: USART implementation on page
RM0461 Rev 5
21 20 19 18
DEDT[4:0]
rw rw rw rw
5 4 3
RXNEI
IDLEIE TE RE
E
rw rw rw rw
1017.
RM0461
17 16
rw rw
2 1 0
UESM UE
rw rw
1017.