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M16C/64C Group
16. DMAC
16.1
Introduction
The direct memory access controller (DMAC) allows data to be transferred without CPU intervention.
There are four DMAC channels. Each time a DMA request occurs, the DMAC transfers one (8- or 16-bit)
unit of data from the source address to the destination address. The DMAC uses the same data bus used
by the CPU. Because the DMAC has higher priority for bus control than the CPU, and because it makes
use of a cycle steal method, it can transfer 1 word (16 bits) or 1 byte (8 bits) of data within a very short
time after a DMA request is generated. Table 16.1 lists DMAC Specifications, and Figure 16.1 shows the
DMAC Block Diagram.
Table 16.1
DMAC Specifications
Item
Number of channels
Transfer memory spaces
Maximum number of bytes
transferred
DMA request sources
Channel priority
Transfers
Transfer address direction
Single transfer
Transfer
mode
Repeat transfer
DMA interrupt request
generation timing
DMA transfer start
DMA
Single transfer
transfer
stop
Repeat transfer When the DMAE bit is set to 0 (disabled)
Reload timing for forward
address pointer and DMAi
transfer counter
DMA transfer cycles
i = 0 to 3
Note:
1.
The selectable sources of DMA requests differ for each channel.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
4 (cycle steal method)
•
From a given address in a 1 MB space to a fixed address
•
From a fixed address to a given address in a 1 MB space
•
From a fixed address to a fixed address
128 KB (with 16-bit transfers) or 64 KB (with 8-bit transfers)
43 sources
Falling edge of INT0 to INT7 (8)
Both edge of INT0 to INT7 (8)
Timer A0 to timer A4 interrupt request (5)
Timer B0 to timer B5 interrupt request (6)
(1)
UART0 to UART2, UART5 to 7 transmission interrupt request (6)
UART0 to UART2, UART5 to 7 reception/ACK interrupt request (6)
SI/O3, SI/O4 interrupt request (2)
A/D conversion interrupt request (1)
Software trigger (1)
DMA0 > DMA1 > DMA2 > DMA3 (DMA0 takes precedence)
8 bits or 16 bits
Forward or fixed (The source and destination addresses cannot both be in the forward
direction.)
Transfer is completed when the DMAi transfer counter underflows.
When the DMAi transfer counter underflows, it is reloaded with the value of the DMAi
transfer counter reload register, and DMA transfer continues.
When the DMAi transfer counter underflows
Data transfer is initiated each time a DMA request is generated when the DMAE bit in
the DMiCON register is 1 (enabled).
•
When the DMAE bit is set to 0 (disabled)
•
After the DMAi transfer counter underflows
When a data transfer is started after setting the DMAE bit to 1 (enabled), the forward
address pointer is reloaded with the value of the SARi or DARi register (whichever is
specified to be in the forward direction), and the DMAi transfer counter is reloaded with
the value of the DMAi transfer counter reload register.
Minimum 3 cycles between SFR and internal RAM
Specification
16. DMAC
Page 234 of 807
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