Read Interface; Relation Between Cpu Clock Frequency And Flash Memory Read Time; Table 5. Number Of Wait States According To Cpu Clock (Hclk) Frequency - ST STM32F446 Series Reference Manual

Embedded Flash memory interface
3.4

Read interface

3.4.1

Relation between CPU clock frequency and Flash memory read time

To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the Flash access control register (FLASH_ACR) according to the
frequency of the CPU clock (HCLK) and the supply voltage of the device.
The prefetch buffer must be disabled when the supply voltage is below 2.1 V. The
correspondence between wait states and CPU clock frequency is given in
Note: On STM32F446xx devices:
- when VOS[1:0] = '0x01', the maximum value of f
- when VOS[1:0] = '0x10', the maximum value of f
168 MHz by activating the over-drive mode.
- when VOS[1:0] = '0x11, the maximum value of f
180 MHz by activating the over-drive mode. The over-drive mode is not available when V
ranges from 1.8 to 2.1 V (refer to
activate the over-drive mode).

Table 5. Number of wait states according to CPU clock (HCLK) frequency

Wait states (WS)
(LATENCY)
0 WS (1 CPU cycle)
1 WS (2 CPU cycles)
2 WS (3 CPU cycles)
3 WS (4 CPU cycles)
4 WS (5 CPU cycles)
5 WS (6 CPU cycles)
6 WS (7 CPU cycles)
7 WS (8 CPU cycles)
8 WS (9 CPU cycles)
After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the
FLASH_ACR register.
It is highly recommended to use the following software sequences to tune the number of
wait states needed to access the Flash memory with the CPU frequency.
66/1328
Voltage range
2.7 V - 3.6 V
0 < HCLK ≤ 30
30 < HCLK ≤ 60
60 < HCLK ≤ 90
90 < HCLK ≤ 120
120 < HCLK ≤ 150 96 < HCLK ≤ 120
150 < HCLK ≤ 180 120 < HCLK ≤ 144
144 < HCLK ≤ 168
168 <HCLK ≤ 180
RM0390 Rev 4
HCLK
HCLK
HCLK
Section 5.1.3: Voltage regulator
HCLK (MHz)
Voltage range Voltage range
2.4 V - 2.7 V
0 <HCLK ≤ 24 0 <HCLK ≤ 22
24 < HCLK ≤ 48 22 < HCLK ≤ 44
48 < HCLK ≤ 72 44 < HCLK ≤ 66
72 < HCLK ≤ 96 66 < HCLK ≤ 88
88 < HCLK ≤ 110
110 < HCLK ≤ 132
132 < HCLK ≤ 154
154 <HCLK ≤ 176
176 <HCLK ≤ 180
Table
is 120 MHz.
is 144 MHz. It can be extended to
is 168 MHz. It can be extended to
for details on how to
Voltage range
1.8 V - 2.1 V
2.1 V - 2.4 V
Prefetch OFF
0 < HCLK ≤ 20
20 < HCLK ≤ 40
40 < HCLK ≤ 60
60 < HCLK ≤ 80
80 < HCLK ≤ 100
100 < HCLK ≤ 120
120 < HCLK ≤ 140
140 < HCLK ≤ 160
160 < HCLK ≤ 168
RM0390
5.
DD