Interrupt Control; I Flag; Ir Bit - Renesas R8C/Tiny Series Software Manual

Chapter 5 Interrupt

5.2 Interrupt Control

The following explains how to enable/disable maskable interrupts and set acknowledge priority. The expla-
nation here does not apply to non-maskable interrupts.
Maskable interrupts are enabled and disabled by using the I flag, IPL, and ILVL2 bits to ILVL0 bits of each
interrupt control register. Whether there is any interrupt requested is indicated by the IR bit of each interrupt
control register.
For details about the memory allocation and the configuration of interrupt control registers, refer to the
R8C's Hardware Manual.

5.2.1 I Flag

The I flag is used to disable/enable maskable interrupts. When the I flag is set to 1 (enabled), all
maskable interrupts are enabled; when the I flag is cleared to 0 (disabed), they are disabled.
When the I flag is changed, the altered flag status is reflected in determining whether or not to accept an
interrupt request at the following timing:
• If the flag is changed by an REIT instruction, the changed status takes effect beginning with that
REIT instruction.
• If the flag is changed by an FCLR, FSET, POPC, or LDC instruction, the changed status takes
effect beginning with the next instruction.
When changed by REIT instruction
Interrupt request generated
When changed by FCLR, FSET, POPC, or LDC instruction
Interrupt request generated
Figure 5.2.1 Timing at which changes of I flag are reflected in interrupt handling

5.2.2 IR Bit

The IR bit is set to 1 (interrupt request issued) when an interrupt request is generated. The IR bit is
cleared to 0 (no interrupt request issued)after the interrupt request is acknowledged and the program
brances to corresponding interrupt vector table.
The IR bit can be cleared to 0 by program. Do not set to 1.
Determination whether or not to
accept interrupt request
Previous
REIT
instruction
(If I flag is changed from 0 to 1 by REIT instruction)
Previous
FSET I
instruction
(If I flag is changed from 0 to 1 by FSET instruction)
Ti m e
Interrupt sequence
Determination whether or not to
accept interrupt request
Interrupt sequence
Next instruction
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5.2 Interrupt Control
Ti m e