I 2 C0 Clock Control Register (S20 Register); Bits 0 To 4: Scl Frequency Control Bits (Ccr0-Ccr4); Bit 5: Scl Mode Specification Bit (Fast Mode); Bit 6: Ack Bit (Ackbit) - Renesas M16C FAMILY series Hardware Manual

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
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16.3 I C0 Clock Control Register (S20 register)
The S20 register is used to set theACK control, SCL mode and the SCL frequency.
16.3.1 Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4)
These bits control the SCL frequency. See Table 16.3 .

16.3.2 Bit 5: SCL Mode Specification Bit (FAST MODE)

The FAST MODE bit selects SCL mode. When the FAST MODE bit is set to "0", standard clock mode
is entered. When it is set to "1", high-speed clock mode is entered.
When using the high-speed clock mode I
set the FAST MODE bit to "1" (select SCL mode as high-speed clock mode) and use the I
system clock (V
IIC

16.3.3 Bit 6: ACK Bit (ACKBIT)

The ACKBIT bit sets the SDA status when an ACK clock
to "0", ACK is returned and te clock applied to SDA becomes "L" when ACK clock is generated. When
it is set to "1", ACK is not returned and the clock clock applied to SDA maintains "H" at ACK clock
generation.
When the ACKBIT bit is set to "0", the address data is received. When the slave address matches with
the address data, SDA becomes "L" automatically (ACK is returned). When the slave address and the
address data are not matched, SDA becomes "H" (ACK is not returned).
NOTES:
1. ACK clock: Clock for acknowledgment

16.3.4 Bit 7: ACK Clock Bit (ACK-CLK)

The ACK-CLK bit set a clock for data transfer acknowledgement. When the ACK-CLK bit is set to "0",
ACK clock is not generated after data is transferred. When it is set to "1", a master generates ACK
clock every one-bit data transfer is completed. The device, which transmits address data and control
data, leave SDA pin open (apply "H" signal to SDA) when ACK clock is generated. The device which
receives data, receives the generated ACKBIT bit.
NOTES:
1.Do not rewrite the S20 register, other than the ACKBIT bit during data transfer. If data is written
to other than the ACKBIT bit during transfer, the I
not be transferred successfully.
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
) at 4 MHz or more frequency.
page 260
f o 3 8 5
2
C bus standard (400 kbits/s maximum) to connect buses,
(1)
is generated. When the ACKBIT bit is set
2
C bus clock circuit is reset and the data may
2
16. MULTI-MASTER I C bus INTERFACE
2
C bus