I2C0 Clock Control Register (S20) - Renesas M16C/64C User Manual

M16C/64C Group
25.2.5

I2C0 Clock Control Register (S20)

I2C0 Clock Control Register
b7 b6 b5 b4 b3 b2 b1
CCR4 to CCR0 (Bit rate control bit) (b4-b0)
Assuming the CCR value (3 to 31) is the value set to bits CCR4 to CCR0, the bit rate can be
calculated using the following equation:
Refer to 25.3.1.2 "Bit Rate and Duty Cycle" for more details.
In standard-speed clock mode,
Bit rate
= ---------------------------------------- -
8 CCR value
When the CCR value is other than 5 in fast-mode,
Bit rate
= ---------------------------------------- -
4 CCR value
When the CCR value is 5 in fast-mode, the bit rate is assumed to reach 400 kbps, the maximum bit
rate in fast-mode.
Bit rate ---------------------------------------- -
=
2 CCR value
Do not set the CCR value from 0 to 2 regardless of the fVIIC frequency.
Rewrite bits CCR4 to CCR0 when the ES0 bit in the S1D0 register is 0 (disabled).
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
Symbol
b0
S20
Bit Symbol Bit Name
CCR0
CCR1
CCR2 Bit rate control bit
CCR3
CCR4
SCL mode select bit
FASTMODE
ACKBIT ACK bit
ACKCLK ACK clock bit
fVIIC
≤
100 kbps
×
fVIIC
≤
400 kbps
×
fVIIC
fVIIC
≤
400 kbps
= ------------- -
×
10
25. Multi-master I
Address
02B4h
Function
Refer to bits CCR4 to CCR0 (Bit Rate
Control Bit) (b4 to b0) in the next page.
0: Standard-speed clock mode
1: Fast-mode
0: ACK is returned
1: ACK is not returned
0: No ACK clock present
1: ACK clock present
2
C-bus Interface
Reset Value
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
Page 543 of 807