Hardware Flow Control; Figure 234. Reception Using Dma; Figure 235. Hardware Flow Control Between 2 Usarts - ST STM32F410 Reference Manual

Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit-
Error flagging and interrupt generation in multibuffer communication
In case of multibuffer communication if any error occurs during the transaction the error flag
will be asserted after the current byte. An interrupt will be generated if the interrupt enable
flag is set. For framing error, overrun error and noise flag that are asserted with RXNE in
case of single byte reception, there will be separate error flag interrupt enable bit (EIE bit in
the USART_CR3 register), which if set will issue an interrupt after the current byte with
either of these errors.
24.4.14

Hardware flow control

It is possible to control the serial data flow between 2 devices by using the nCTS input and
the nRTS output. The
RTS and CTS flow control can be enabled independently by writing respectively RTSE and
CTSE bits to 1 (in the USART_CR3 register).
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Figure 234. Reception using DMA

Figure 235 shows how to connect 2 devices in this mode:

Figure 235. Hardware flow control between 2 USARTs

RM0401 Rev 3